Comparative analysis of radiation effects on the electroluminescence of Si and SiGe/Si(001) heterostructures with self-assembled Islands

The effect of neutron radiation on the electroluminescence of the Si p-i-n diode containing a multilayered Ge/Si heterostructure with self-assembled nanoislands is studied. In comparison with bulk Si, the diodes containing Ge(Si) nanoislands exhibit a higher radiation hardness of the electroluminescence signal, which is attributed to spatial localization of charge carriers in the Ge/Si nanostructures. The spatial localization of charge carriers impedes their diffusion to radiation defects followed by nonradiative recombination at the defects. The results show the possibilities of using Ge/Si heterostructures with self-assembled nanoislands for the development of optoelectronic devices resistant to radiation.     

Novel and Simple Solution-processed MIS Ultraviolet (UV) Detector Based on Core–Shell Si/SiO2 Nanocrystals

In the present study, we report a simple and solution-processed visible blind metal–insulator–semiconductor (MIS) ultraviolet (UV) detector based on core–shell Si/SiO₂ nanocrystals that are fabricated on interdigitated electrodes. The fabricated photo detector shows high photosensitivity in the UV-B and UV-C wavelength ranges. The absorption spectra of the nano-structured materials used in this work is simulated by the density functional theory (DFT) method and analyzed based on the electronic structure. It is then compared with the experimental results. The synthesized nano materials show very low density of structural defects based on the measured photoluminescence spectra, which results in a fast response time for the fabricated photodetector. Compared to the previously reported similar Si/SiO₂-based photo-detectors, the fabricated detector shows very good photo responsivity.     

Graphene/SiO2/p‐GaN Diodes: An Advanced Economical Alternative for Electrically Tunable Light Emitters

Advanced materials that combine novel functionality and ease of applicability are central to the development of light‐emitting diodes (LEDs), which is of ever increasing commercial importance. Here a new metal‐insulator‐semiconductor (MIS) LED structure that combines economical fabrication with novel device properties is reported. The presented MIS‐LED consists of a graphene electrode on p‐GaN substrate separated by an insulating SiO₂ layer. It is found that the MIS‐LED possesses a unique tunability of the electroluminescence spectra depending on the bias conditions. Tunnel injection from graphene into the p‐GaN can explain the difference in luminescence spectra under forward and reverse bias. The demonstrated MIS‐LED expands the use of graphene and also possibly allows the direct integration of light emitters with other circuit elements.     

Controlling the electrical characteristics of Au/n-Si structures by interfacial insulator layer

Admittance (C–V and G/ω–V) measurements of Au/n-Si (metal–semiconductor, MS) and Au/SnO₂/n-Si (metal–insulator–semiconductor, MIS) structures were carried out between 1 kHz and 1 MHz at room temperature to investigate the interfacial insulator layer effect on the electrical characteristics of Au/n-Si structures. Experimental results showed that MIS structure's capacitance (C) values, unlike those of MS structure, became stable especially at high frequencies in the accumulation region. Also, the insulator layer caused structure's shunt resistance (R_sh) to increase. It was found that series resistance (R_s) is more effective in the accumulation region at high frequencies after the correction was applied to C and G/ω data to eliminate the R_s effect. The density of interface states (D_is) was obtained using Hill–Coleman method, D_is values MIS structure was obtained smaller than those of MS structure. Results indicate that interfacial insulator layer brings about some improvements in electrical characteristics of Au/n-Si structures.     

MISFET structures with barium titanate as a dielectric layer for application in memory cells

This work shows investigations of La₂O₃ containing BaTiO₃ thin films deposited on Si substrates by Radio Frequency Plasma Sputtering (RF PS) of sintered BaTiO₃ + La₂O₃ (2 wt.%) target. Round, aluminum (Al) electrodes were evaporated on top of the deposited layers. Thus, metal–insulator–semiconductor (MIS) structures were created with barium titanate thin films playing the role of an insulator. The MIS structures enabled a subsequent electrical characterization of the studied film by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements. Several electronic parameters, i.e., ε_ri, ρ, V_FB, ΔV_H were extracted from the obtained characteristics. Moreover, the paper describes technology process of MISFETs fabrication and possibility of their application as memory cells. The influence of voltage stress on transfer and output I–V characteristics of the transistors are presented and discussed.     

Compliance current dominates evolution of NiSi2 defect size in Ni/dielectric/Si RRAM devices

Resistive random access memory (RRAM) devices with a nickel top electrode form controllable metal nanofilaments and have robust resistive switching performance. We investigate the Ni/HfO₂/SiO_x/n⁺ Si RRAM structure, which forms a Ni-rich defect in the silicon underneath the Ni nanofilament in the dielectric layers after a SET process. The formation of these defects may affect the retention of the devices, so we applied a detailed Finite Element Method and Kinetic Monte Carlo approach to simulate the Ni-rich defect evolution under different compliance current settings. We confirm that the chemical composition of the defects is metallic NiSi₂, and that their size is determined by the compliance current. These simulation results are supported by in-situ STM-like experiments inside a transmission electron microscope (TEM). NiSi₂ defects are shaped as truncated square pyramids, and we show that this is due to the low activation energy of Ni migration along the (111) crystal plane of Si. Our results demonstrate that electromigration is the main driving force for Ni migration initially, after which thermal migration and especially stress migration become the dominant mechanism. This work gives a fascinating example of an as-grown metal–insulator–semiconductor (MIS) system that can be controllably converted to a metal–insulator–metal (MIM) configuration for down-scaled RRAM operation.     

Physical properties of metal–insulator–semiconductor structures based on <Emphasis Type="Italic">n</Emphasis>-GaAs with InAs quantum dots deposited onto the surface of an <Emphasis Type="Italic">n</Emphasis>-GaAs layer

The properties of metal–insulator–semiconductor (MIS) structures based on n-GaAs in which silicon oxide and yttria-stabilized zirconia and hafnia are used as the insulator containing InAs quantum dots, which are embedded at the insulator/n-GaAs interface, are investigated. The structures manifest the resistive switching and synaptic behavior.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

Single‐Electron Tunneling through Molecular Quantum Dots in a Metal‐Insulator‐Semiconductor Structure

A sigle‐electron tunneling (SET) in a metal‐insulator‐semiconductor (MIS) structure is demonstrated, in which C₆₀ and copper phthalocyanine (CuPc) molecules are embedded as quantum dots in the insulator layer. The SET is found to originate from resonant tunneling via the energy levels of the embedded molecules, (e.g., the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO)). These findings show that the threshold voltages for SET are tunable according to the energy levels of the molecules. Furthermore, SET is observable even near room temperature. The results suggest, together with the fact that these properties are demonstrated in a practical device configuration, that the integration of molecular dots into the Si‐MIS structure has considerable potential for achieving novel SET devices. Moreover, the attempt allows large‐scale integration of individual molecular functionalities.     

Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion—I. Theory

If the insulating layer in a metal-insulator-semiconductor (MIS) diode is very thin ($\text{<60}\text{A}\text{?}$ for AlSiO₂Si), measureable tunnel current can flow between the metal and the semiconductor. If the insulating layer is even thinner ($\text{<30}\text{A}\text{?}$), tunnel currents are so large that they can significantly disturb the semiconductor from thermal equilibrium. Under such conditions, MIS diodes exhibit properties determined by which of the following tunneling processes is dominant; tunneling between the metal and the majority carrier energy band in the semiconductor, between the metal and the minority carrier energy band, or between the metal abd surface state levels. In the present paper, minority carrier MIS tunnel diodes are analysed using a very general formulation of the tunneling processes through the insulator, transport properties in the semiconductor, and surface state effects. Starting from solutions for diodes with relatively thick insulating layers where the semiconductor is essentially in thermal equilibrium, solutions are obtained for progressively thinner insulating layers until non-equilibrium effects in the semiconductor are observed. It is shown that such minority carrier MIS tunnel diodes with very thin insulating layers possess properties similar to p-n junction diodes including exponential current-voltage characteristics which approach the “ideal diode” law of p-n junction theory. The theory adequately describes the observed properties of experimental devices reported in a companion paper. The diodes have application as injecting contacts, as photodiodes or elements of photodiode arrays, and as energy conversion devices employing the electron- or photo-voltaic effects.     

Frequency response of the current multiplication process in MIS tunnel diodes

In contrast to thick insulator structures, metal-insulator-semiconductor (MIS) diodes with very thin insulating regions (<30 Å for the metal-silicon dioxide-silicon system) allow appreciable tunnel current flow between the metal and the semiconductor. Under such conditions, it has recently been shown that multiplication of minority carriers supplied to the contact region can be obtained if the work function of the metal contact is suitably chosen. This paper reports the first quantitative experimental measurements of this multiplication process and its frequency dependence. Gains in the range 100–1000 are reported for AlSiO₂Si devices but the frequency response of the gain mechanism for these devices is found to be relatively restricted, measured values being in the 10 kHz range.     

Electrical Properties and Current Transport Mechanisms of the Au/n-GaN Schottky Structure with Solution- Processed High-k BaTiO3 Interlayer

The electrical properties and current transport mechanisms of Au/BaTiO₃ (BTO)/n-GaN metal–insulator–semiconductor (MIS) structures have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements at room temperature. Experimental results reveal that the MIS structure has a higher rectification ratio with low reverse leakage current compared with the Au/n-GaN metal–semiconductor (MS) structure. The calculated barrier height of the Au/BTO/n-GaN MIS structure [0.87 eV (I–V)/1.02 eV (C–V)] increases compared with the Au/n-GaN MS structure [0.73 eV (I–V)/0.96 eV (C–V)]. The series resistance is extracted using Cheung’s functions, and the values are in good agreement with each other. Furthermore, the energy distribution of the interface state density is estimated from the forward-bias I–V data. It is noteworthy that the interface state density of the MIS structure is lower than that of the MS structure. In both MS and MIS structures under forward-bias conditions, ohmic and space-charge-limited conduction mechanisms are identified at lower and higher voltages, respectively. Investigations reveal that Poole–Frenkel emission dominates the reverse leakage current in both Au/n-GaN and Au/BTO/n-GaN structures.     

Fully coherent Ge islands growth on Si nano-pillars by selective epitaxy

Our recent experimental results of Ge nanoheteroepitaxy (NHE) on Si nanopillars (NPs) are reviewed to confirm the possibility of relaxed Ge growth on Si without misfit dislocations (MDs) formation by elastic deformation. Selective Ge growth is performed by using reduced pressure chemical vapor deposition (CVD) on two types of Si NPs with thermal SiO₂ or CVD SiO₂ sidewalls and on Si nanoislands (NIs) on SiO₂. By using thermal SiO₂ sidewall, compressive strain is generated in the Si pillar and fixed by the thermal SiO₂. This results in an incoherent Ge growth on Si NPs due to MD formation. By using CVD SiO₂ sidewall, tensile strain formation due to thermal expansion during prebake for Ge epi process is observed. However, strain in Si due to Ge growth is not dominant. By introducing a Si_0.5Ge_0.5 buffer layer, no MD and stacking faults are observed by cross section TEM. The shape of Ge on Si NPs becomes more uniform due to improved crystal quality. On Si NIs on SiO₂, a clear compliance effect is observed after Ge growth. Coherent growth of Ge on Si is also realized on Si NIs by using Si_0.5Ge_0.5 buffer.     

Electronic Contact Deposition onto Organic Molecular Monolayers: Can We Detect Metal Penetration?

Using a semiconductor as the substrate to a molecular organic layer, penetration of metal contacts can be clearly identified by the study of electronic charge transport through the layer. A series of monolayers of saturated hydrocarbon molecules with varying lengths is assembled on Si or GaAs and the junctions resulting after further electronic contact is made by liquid Hg, indirect metal evaporation, and a “ready‐made” metal pad are measured. In contrast to tunneling characteristics, which are ambiguous regarding contact penetration, the semiconductor surface barrier is very sensitive to any direct contact with a metal. With the organic monolayer intact, a metal–insulator–semiconductor (MIS) structure results. If metal penetrated the monolayer, the junction behaves as a metal–semiconductor (MS) structure. By comparing a molecule‐free interface (MS junction) with a molecularly modified one (presumably MIS), possible metal penetration is identified. The major indicators are the semiconductor electronic transport barrier height, extracted from the junction transport characteristics, and the photovoltage. The approach does not require a series of different monolayers and data analysis is quite straightforward, helping to identify non‐invasive ways to make electronic contact to soft matter.     

Analytical investigation of surface potential and related properties of metal/insulator/III–V semiconductor capacitors

An analytical study of the effect of an applied gate bias on the potential and electron density in the semiconductor of metal/insulator/III–V semiconductor (III–V MIS) capacitors is carried out. For this, Poisson's equation is rewritten to a form amenable to analytical study. Si₃N₄ is used as an insulator layer for the MIS capacitors. In order to highlight the advantages of III–V MIS capacitors over metal-SiO₂---Si (MOS) capacitors, the ideal case free from interface traps is considered and theoretical results are obtained also for MOS capacitors. The calculated results strongly demonstrate the superiority of InGaAs MIS and GaAs MIS capacitors to Si MOS capacitors and pinpoint the situation in which the interface states are present.     

Recent progress in MIS solar cells

Metal–insulator–semiconductor (MIS)-type solar cells have an inherent cost advantage compared to p-n junction solar cells. First-generation MIS–inversion layer (MIS–IL) solar cells, already successfully produced in an industrial pilot line, are restricted to efficiencies of 15–16%. With the second-generation MIS–IL silicon solar cells, based on drastically improved surface passivation by plasma-enhanced chemical vapour-deposited silicon nitride, simple technology can be combined with very high efficiencies. The novel inversion layer emitters have the potential to outperform conventional phosphorus-diffused emitters of Si solar cells. A 17.1% efficiency could already be achieved with the novel point-contacted ‘truncated pyramid’ MIS–IL cell. A new surface-grooved line-contact MIS–IL device presently under development using unconventional processing steps applicable for large-scale fabrication is discussed. By the mechanical grooving technique, contact widths down to 2 μm can be achieved homogeneously over large wafer areas. Bifacial sensitivity is included in most of the MIS-type solar cells. For a bifacial 98 cm² Czochralski (Cz) Si MIS-contacted p-n junction solar cell with a random pyramid surface texture and Al as grid metal, efficiencies of 16.5% for front and 13.8% for rear side illumination are reported. A 19.5% efficiency has been obtained with a mechanically grooved MIS n⁺p solar cell. The MIS-type silicon solar cells are able to significantly lower the costs for solar electricity due to the simple technology and the potential for efficiencies well above 20%.©1997 John Wiley & Sons, Ltd.     

Selective etching of Si,SiGe, Ge and its usage for increasing the efficiency of silicon solar cells

Dependences of the etch rates for KOH and HF:H₂O₂:CH₃COOH solutions on SiGe layer composition were investigated. The obtained results has been proposed to use for formation of the submicron relief on the silicon surface via selective etching of the structures with Ge(Si) self-assembled nanoislands. In the framework of the proposed approach the Ge(Si) nanoislands serve as a mask for selective etching of Si in a mixture of an aqueous solution of KOH with isopropyl alcohol, followed by the islands removal from the surface by the selective etching in HF:H₂O₂:CH₃COOH. It was demonstrated experimentally that such approach allows to produce the submicron relief on a silicon surface, which leads to the significant decrease of the reflectivity in a wide spectral range. It is believed that the proposed method of surface relief formation can be used to improve the efficiency of the thin-film solar cells based on the crystalline silicon.     

Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Current-voltage characteristics of Al/SiO2/p-Si MOS tunnel diodes with a spatially nonuniform oxide thickness

The effect of nonuniform distribution of the insulator thickness on the behavior of Al/SiO₂/p-Si MOS tunnel structures with a (1–4)-nm-thick insulator is studied. The character and magnitude of the effect depend on the applied bias. In any conditions, the nonuniformity of the SiO₂ thickness enhances the total through currents as compared to those flowing across a uniform oxide layer of the same nominal thickness. Further, the potential of the inversion layer changes in the inversion mode. The calculations performed take into account the tunnel transport between the Si conduction band and the metal, that between the Si valence band and the metal (including in the inversion mode, the resonant transport, which is less clearly pronounced because of the thickness nonuniformity), and the band-to-band tunneling in the semiconductor.