一种ADC积分非线性参数内建自测试方案

针对ADC(模数转换器)静态参数中积分非线性参数测试的问题,提出了一种快速测试的内建自测试方案。该方案利用数字谐振器和Σ-Δ调制器生成正弦测试源信号,依据FFT算法建立ADC的切比雪夫函数逼近模型,进而根据数学模型快速计算积分非线性参数。与传统的码密度直方图测试方案相比,所提出内建自测试方案硬件开销小,测试速度快,易于片上集成。实验结果验证了该方案的有效性。     

一种6-bit 3-Gsps GaAs HBT模数转换器

本文介绍了一种采用1 μm InGaP/GaAs HBT工艺实现的6-bit 3-Gsps模数转换器的设计和测试结果。这款单片折叠内插模数转换器采用高线性度的跟踪保持放大器提高了有效分辨率ENOB。该模数转换器的芯片尺寸为4.32 mm×3.66 mm。测试结果表明,该模数转换器在3-Gsps采样率的情况下,ENOB达到5.53,有效分辨率带宽为1.1 GHz,差分非线性误差和积分非线性误差的最大值分别为0.36 LSB和0.48 LSB。     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器. 测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB. 模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB. 电路采用0.18μm 混合信号CMOS工艺实现,芯片面积为0.76mm2.     

采用改进型1.5位/级结构的10位100MHz流水线模数转换器

介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB.模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB.电路采用0.18μm混合信号CMOS工艺实现,芯片面积为0.76mm2.     

红外焦平面列级ADC数字读出电路测试技术研究

数字化红外焦平面器件是焦平面发展的重要方向,其核心是读出电路集成高性能模数转换器(ADC)。分析了读出电路数字化输出后焦平面性能参数的评价方法,阐述了红外焦平面列级ADC的静态测试和动态测试方法,提出了基于斜坡电压输入的过采样原理测试ADC静态性能,提升无误码分辨率测试正确性。针对ADC静态测试和动态测试要求,结合Labview软件和数字采集卡搭建了软硬件测试平台,并通过一款数字焦平面芯片的测试,验证了测试方法和平台适用于行列级ADC数字化读出电路的测试评价。     

基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。     

SOC芯片中高速ADC的测试方法

本文简单描述了SOC芯片测试技术,模数转换器(ADC)是SOC芯片中的重要模块,随着器件时钟频率的不断提高,如何高效、准确地测试ADC的动态参数和静态参数是当今SOC芯片中的ADC测试研究重点.本文重点介绍了一款SOC芯片中高速ADC测试的方法.     

基于IP核的SOC中ADC的测试技术

本文简单描述了SOC芯片测试技术的复杂性，模数转换器（ADC）是SOC芯片中的重要模块，随着器件时钟频率的不断提高，高效、准确地测试ADC的动态参数和静态参数是当今SOC芯片中的ADC测试研究重点。本文重点介绍了一款SOC芯片中高速ADC测试的方法。     

高精度混合集成电路直方图测试讨论

推演了模数转换器（ADC）的直方图测试方法，主要推导ADC的主要静态参数。通过以传统定义法测试和直方图法测试进行ATE测试对比。选取AD7656型号通过以ADVANTEST T2000为平台进行直方图测试，和以ADVANTEST T6575为平台进行传统定义法测试，对比四项参数测试数据，并对两种算法测试优劣进行比对。     

高速模数转换器动态非线性检测的双谱方法

本文提出了利用双谱分析高速模数转换器（ＡＤＣ）动态非线性的方法，指出双谱方法可以明显地减小量化噪声对谐波分析的影响，提出动态非线性测量的灵敏度和精度。计算机模拟测试结果表明，双谱法比功率法具有高的检测分辨率的抗噪声能力。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.     

一种新的多值A/D转换器

通过对三值 A/ D转换数学表示的分析 ,设计了二种三值 A/ D转换器电路。该转换器电路具有结构简单、低功耗、小型化和高信息密度等优点 ,它可进一步完善多值数字系统的研究     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.