Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection

A calibration methodology for the optimized minimum inductor (OMI) bandpass filter (BPF) to compensate passive components' inherent loss, such as resistances and reactances, is presented. OMI BPF prevails conventional elliptic and Chebyshev BPFs by introducing fewer inductors for the same stopband rejection requirement. Given design specifications (bandwidth, stopband rejection) at a specific center frequency, the calibration flow optimizes the approach to offset the inaccuracy of center frequency, bandwidth, and stopband rejection due to the discrepancy between the actual and ideal prototype passive components. Two OMI BPF designs before and after calibration are presented for demonstration and comparison. They are 1) a 3rd order centered at 2.388 GHz, 35.54% fractional bandwidth (FBW), 29.97 dB stopband rejection, and 2) a 7th order centered at 2.333 GHz, 17.40% FBW, 62.29 dB stopband rejection.     

Multiband BPF with wide upper stop band using asymmetrically positioned stub loaded open loop resonators

In this paper, asymmetrically positioned stub loaded open loop resonators with pseudo interdigital coupling are used to design compact multiband planar bandpass filters. The first design pertains to a dualband BPF that operates at 3.5 GHz and 5.7 GHz. The parameters like position of stub, which quantifies the asymmetry, and length of stub are further optimised using real coded genetic algorithm to evolve a triband BPF. The evolutionary design procedure is supported with an example of triband BPF having passband at 3.5 GHz, 5.5 GHz and 6.8 GHz, respectively. The transmission line models for both filters are developed as well as fabricated prototypes are realised and tested. There is a good agreement between the measured and simulated results. The measured insertion loss at first and second band centred around 3.5 GHz and 5.7 GHz of the dual band BPF are 1.5 dB and 1.25 dB, respectively. For the triband BPF the values are 1.24 dB, 1.6 dB and 1.8 dB at 3.5, 5.5 and 6.8 GHz, respectively. The dualband design covers the WiMAX and IEEE 802.11a bands where as the triband design also covers the 6.8 GHz RFID frequency.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

采用新型可调谐有源电感的频率可调谐高Q低噪声的带通滤波器

对采用双回转结构交叉耦合差分有源电感(DGC-DAI)的可调谐、高品质因子Q和低噪声差分有源带通滤波器(THQLNA-BPF)进行了研究。输入级,采用差分共基-共射结构,以抑制噪声和获得高频特性;输出级,采用差分共集放大器,以获得高的驱动能力和高的隔离度;有源电感滤波网络,利用DAI电感值可宽范围调谐、高Q值和低的噪声,来分别实现BPF的中心频率的宽范围调节、高Q值和良好的噪声特性;进一步地,利用变容二极管网络改善BPF中心频率的可调性和提高Q值,利用有源可调负阻网络提高BPF的Q值和进行Q值独立调节。基于WIN 0.2μm GaAs HBT工艺,利用ADS对THQLNA-BPF进行性能验证。结果表明:中心频率可在1.68 GHz~4.32 GHz范围内调谐,调谐量达2.64 GHz;最大和最小Q分别达到83.6和33.6;噪声范围为6.04 dB~8.83 dB;在中心频率为3.69 GHz时,输入1 dB压缩点为-7.3 dBm,稳定系数μ>1;静态功耗小于18 mW。     

A UHF current-mode continuous-time band-pass delta sigma modulator using fully balanced active inductor

This paper introduces a 2 GHz continuous-time (CT) fourth order current-mode (CM) band-pass 0.18 μm CMOS delta sigma modulator (DSM) utilizing a fully balanced active inductor. The proposed active inductor takes advantage of positive feedback topology and features accurate loss compensation as well as independent tunability of quality factor and resonant frequency. Based on this active inductor, a CM Ultra High Frequency (UHF) resonator is also proposed, exhibiting a very small on-chip area. Moreover, a high speed CM quantizer working with one single clock is brought into eliminate the error introduced by clock generators. The post layout simulation of the DSM exhibits a peak SNDR of 43.6 dB at 500 MHz with a 40 MHz signal bandwidth while the center frequency can be tuned between 450 and 500 MHz. The measured results give an averaged SNDR of 33 dB with 40 MHz signal bandwidth, where the center frequency is tunable from 300 MHz to 350 MHz. This design consumes only 45 mW under 1.8 V power supply and occupies an area of 0.133 mm².     

Fabrication and performance of novel RF spiral inductors on silicon

This paper presents and discusses the fabrication and the performance of RF circular spiral inductors on silicon. The substrate materials underneath the inductor coil are removed by wet etching process. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure the seed layer and the pillars contact perfectly, and dry etching technique is used to remove the seed layer. The results show that Q-factor of the novel inductor is greatly improved by removing the silicon underneath the inductor coil. The spiral inductor for line width of 50 μm has a peak Q-factor of 17 at frequency of 1 GHz. The inductance is about 3.2 nH in the frequency range of 0.05-3 GHz and the resonance frequency of the inductors is about 6 GHz. If the strip is widened to 80 μm, the peak Q-factor of the inductor reduces to about 10 and the inductance is 1.5 nH in the same frequency range.     

A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor

In this paper, a low flicker-noise, 2.4 GHz direct onversion receiver (DCR) has been designed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor in the mixing stage. The tuning inductor has been replaced by a differential active inductor circuit, which gives the same inductance, with less chip size and high quality factor. The DCR has been designed in a TSMC 0.18 μm 1P6M CMOS process for wireless LAN 802.11g applications. The proposed DCR achieves 6.7 dB SSB-NF, 34 dB conversion gain, −13.5 dBm IIP3, and flicker noise (1/f) corner frequency of 30 kHz with 137.5 mW power consumption from 1.8 V supply voltage.     

Low power and high gain current reuse LNA with modified input matching and inter-stage inductors

In this paper we present a fully integrated current reuse CMOS LNA (low noise amplifier) with modified input matching circuitry and inductive inter-stage architecture in 0.18 μm CMOS technology. To reduce the large spiral inductors that actually require larger surface area for their fabrication, two parallel LC circuits are used with two small spiral on-chip inductors. Using cascode configuration equipped by parallel inter-stage LCs, we achieved lower power consumption with higher power gain. In this configuration we used two cascoded transistors to have a good output swing suitable for low voltage technology compared to other current reuse configurations. This configuration provides better input matching, lower noise figure and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in center frequency of 5.5 GHz, with 1.9 dB NF, 50 Ω input impedance, 1 GHz 3 dB power bandwidth, 20.5 dB power gain (S₂₁), high reverse isolation (S₁₂)<−48 dB, −18.5 dB input matching (S₁₁) and −21.3 dB output matching (S₂₂), while dissipating as low power as 2 mW at 1.8 V power supply.     

A 3.3 mW K-Band 0.18-μ m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P_{1 dB} and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.     

L,S波段高性能窄带有源滤波器的研制

本文研究了一种直接利用晶体管或场效应管来模拟高Ｑ值电感，并利用此电感来制作Ｌ波段和Ｓ波段窄带有源滤波器的方法。利用此方法制作了两个高性能的窄带有源带通滤波器：一个中心频率为２．３ＧＨｚ，其带宽为９０ＭＨｚ左右，带内插入损耗为０ｄＢ；一个中心频率在１．５ＧＨｚ左右，并且中心频率可调，其带宽为８０ＭＨｚ左右，带内有１０ｄＢ的增益     

基于MMIC工艺的片上射频LC无源滤波器

设计、制作了几种基于MMIC工艺的片上LC低通/带通滤波器并进行了测试.测试结果表明,一个3nH的MMIC电感在6.8GHz下品质因数达到13.8.自谐振频率达到15.5GHz;制作的LC低通/带通滤波器的截止频率或中心频率与设计偏差很小,分别为2%和3.3%;低通滤波器在各自通带内的插入损耗小于3dB,带通滤波器在中心频率的插入损耗为7.2dB.     

基于MMIC工艺的片上射频LC无源滤波器

设计、制作了几种基于MMIC工艺的片上LC低通/带通滤波器并进行了测试. 测试结果表明,一个3nH的MMIC电感在6.8GHz下品质因数达到13.8,自谐振频率达到15.5GHz;制作的LC低通/带通滤波器的截止频率或中心频率与设计偏差很小,分别为2%和3.3%;低通滤波器在各自通带内的插入损耗小于3dB,带通滤波器在中心频率的插入损耗为7.2dB.     

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602 MHz for DTV programs. In experiments, the polyphase filter can achieve 85 dB for the image rejection in the center frequency. The main signal can be gained about 2-5 dB without using extra amplifier. The chip size is about 0.09 mm², and the average power dissipation is about 15 mW, when the chip technology employed TSMC 0.35 μm CMOS process. The proposed chip outperforms with less area and higher gain.     

Ultra low voltage, high performance operational transconductance amplifier and its application in a tunable Gm-C filter

This paper presents an ultra low voltage, high performance Operational Transconductance Amplifier (OTA) and its application to implement a tunable Gm-C filter. The proposed OTA uses a 0.5 V single supply and consumes 60 μw. Employing special CMFF and CMFB circuits has improved CMRR to 138 dB in DC. Using bulk driven input stage results in higher linearity such that by applying a 500 mv_p-p sine wave input signal at 2 MHz frequency in unity gain closed loop configuration, third harmonic distortion for output voltage is −46 dB and becomes −42.4 dB in open loop state for 820 mv_p-p output voltage at 2 MHz. DC gain of the OTA is 47 dB and its unity gain bandwidth is 17.8 MHz with 20 pF capacitance load due to both deliberately optimized design and special frequency compensation technique. The OTA has been used to realize a wide tunable Gm-C low-pass filter whose cutoff frequency is tunable from 1.4 to 6 MHz. Proposed OTA and filter have been simulated in 0.18 μm TSMC CMOS technology with Hspice. Monte Carlo and temperature dependent simulation results are included to forecast the mismatch and temperature effects after fabrication process.     

一种适用于多波段无线通信的品质因数增强型的CMOS射频滤波器

提出了一种使用品质因数增强型的有源电感的射频带通滤波器,描述了在宽射频频段上可调谐的品质因数增强型的有源电感设计技术,而且解释了与有源电感噪声和稳定性相关的问题.该滤波器采用0.18μm CMOS工艺制造,它所占用芯片的有效面积仅为150μm×200μm.测试结果表明:该射频滤波器中心频率为2.44GHz时,3dB带宽为60MHz,中心频率可在2.07～2.44GHz范围内调谐,1dB压缩点为-15dBm,而静态功耗为10.8mW;在中心频率为2.07GHz时,滤波器的品质因数可达到103.     

微型化2GHz低噪声高选择性放大模组的研制

本文介绍一种将微波低频段分布参数电路与超微细薄膜工艺结合的微型化、低噪声、高选择性的放大模组。对低噪声放大电路、椭圆函数带通滤波电路及后级平衡放大电路的设计完成后,将其制作在76×20×0.5mm^3氧化铝陶瓷基片上。本模组在1.8-2.2GHz范围内,增益Gp≥50dB,噪声系数Nf≤0.9dB,其1dB压缩点输出功率Po≈30dBm,带外抑制≥80dB。     

On the use of body biasing to improve linearity in low LO-power CMOS active mixers

In a radio-frequency (RF) transceiver, the linearity of the mixer has a profound effect on the overall transceiver performance. In many RF transceivers, active mixers are used due to their higher gain which also improves the overall receiver noise figure. In a typical RF active mixer where the transistors in the LO stage switch abruptly, most of the nonlinear distortions come from the transconductance or RF stage and thus the linearity of the mixer can be enhanced by proper design of the RF stage. In low-power receivers, however, to reduce the power consumption of the local oscillator (LO) circuit, the amplitude of LO signal is low and thus the switching of the transistors in the LO stage of the mixer is gradual. In this paper, we propose a technique to improve the linearity of such low-power mixers by enhancing the linearity of the LO stage. In particular, body biasing is utilized in the LO stage to improve the linearity. To verify the effectiveness of the proposed technique, two proof-of-concept double-balanced down-conversion active mixers have been designed and fabricated in 0.13-µm CMOS. The maximum IIP3 of +2.7 dBm and −4.9 dBm at a conversion gain of 13 dB and 16 dB are achieved for the first and second prototype respectively. For a 2.4 GHz RF input signal and an intermediate-Frequency (IF) of 50 MHz, the first prototype consumes 2.4 mW from a 1.2 V supply while the second one consumes only 780 µW from a 0.7 V supply.     

A 65 nm CMOS fully-integrated dynamic reconfigurable differential power amplifier with high gain in both bands

A fully-integrated dual-band dynamic reconfigurable differential power amplifier with high gain in 65 nm CMOS is presented. A switchable shunt LC network is proposed to implement the dual-band reconfigurable operation and achieve high gain at both low and high frequency bands, and the high quality on-chip transformers are utilized to implement input/output impedance matching and single-ended to differential conversion. Measured results show that the dual-band dynamic reconfigurable power amplifier can provide 23 dB gain at 2.15 GHz and 21 dB gain at 4.70 GHz, and achieve more than 19 dBm saturated output power at 2.15 GHz and 13 dBm saturated output power at 4.70 GHz, respectively. The die area is about 1.7 mm×2.0 mm.     

Design of ultra wideband trapezoidal shape slot antenna with circular polarization

A CPW-feed printed slot antenna with circular polarization characteristics is presented in this paper. The basic structure of the antenna is a rectangular slot excited by a 50 Ω CPW line terminated on a trapezoidal shaped tuning stub. Perturbations in the form of circular stubs are applied in the slot to realize circular polarization. The measured impedance bandwidth (S₁₁ < −10 dB) for the initial design is 4.4 GHz (from 2.2 GHz to 6.6 GHz) while the 3-dB axial ratio bandwidth is 1.77 GHz (from 4 GHz to 5.77 GHz) which is 36.23% at the center frequency of 4.88 GHz. The basic structure of the antenna was further modified to enhance the impedance bandwidth to reach well beyond 12 GHz while increasing the ARBW to 44.3% (from 4.3 GHz to 6.75 GHz). The proposed antenna in its final version has a measured peak gain of about 5 dB throughout the useful band and nearly stable radiation pattern.     

140GHz空腔滤波器设计及加工工艺研究

设计并实现了一种采用进口电火花技术加工的D波段电感膜片耦合的矩形波导空腔滤波器。采用等效电路法设计了一个140GHz矩形空腔带通滤波器。采用有限元仿真软件HFSS分析了腔体个数对滤波器主要性能的影响,最终成功设计了一个性能优良的四阶空腔滤波器,中心频率（140±3）GHz,带内插入损耗S21在-3dB以内,回波损耗S11在-20dB以下。采用电火花微加工技术成功加工出了四阶滤波器的主体部分,相应完成了结构键合等关键工艺,首次制作了基于电火花技术的D波段矩形波导空腔滤波器。测试结果为中心频率（138.5±3）GHz,带内插入损耗最好达到了-4.4dB。结果表明滤波器在140GHz具有带通特性和滤波功能,尽管与理论上的-3dB有差异,但考虑到加工误差、夹具损耗等情况下,样品主要技术指标与设计值较为一致。