一种基于CMOS工艺射频有源滤波器的设计

射频滤波器是无线通信系统的关键部件之一。本文根据射频SoC的需求,设计了一种基于Q-增强型射频有源CMOSLC型滤波器。该滤波器利用负阻抗增强电路品质因数,可有效地解决射频片上无源LC滤波器的品质因数偏低,插入损耗偏大的问题。该滤波器采用TSMC 0．18umCMOS工艺,当供电电压为1．8V,中心频率在2．142GHz时,-3dB带宽仅为36MHz。仿真结果表明,该滤波器正确有效,适于全集成。     

Third-order voltage-mode active-C band pass filter

In this research article, a new third-order voltage-mode active-C asymmetrical band pass filter is proposed. It uses three numbers of current-controlled current conveyors and three numbers of equal-valued capacitors. The topology has the following important features: uses only three active elements, uses three capacitors, uses all grounded capacitors and no resistor is suitable for integrated circuit design, there is no matching constraint, high input impedance, low output impedance, central frequency can easily be electronically controlled by bias current, and frequency response is asymmetrical in nature. The application of the proposed topology in the realisation of a voltage-mode sixth-order symmetrical band pass filter has been demonstrated. The workability of the proposed topology and sixth-order filter has been confirmed by simulation results using 0.35-µm Austria Micro Systems complementary metal oxide semiconductor technology.     

Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer

This paper presents a new design of a grounded active inductor (AI) with an improved topology based on Manetakis regulated cascode active inductor comprising of three control voltages for tunability. An additional pMOST was introduced in the design as a drain load at the output of nMOST source follower. The aim of this work is to design a CMOS AI at Ku band using AIDA-C, a state-of-the-art multi-objective multi-constraint circuit-level optimization tool. Firstly, a reasonable AI operating at Ku band was manually designed using a 130 nm technology. This circuit and its design variables were fed to AIDA-C as an element of the initial population. Then the sizing of the proposed AI MOSTs was optimized. AIDA-C circuit sizing tool is able to achieve not only one but a set of solutions for the AI exhibiting high quality factor at a predefined Ku band operating frequency. This set of alternative Pareto optimal solutions enables the designer to choose the most suitable circuit sizing for a given application. AI’s main performance parameters in terms of s parameters (s₁₁), quality factor (Q), inductance value (L), linearity, noise figure, power consumption and tunability based on control and biasing voltages are presented. Layout of the optimized AI is also presented. This AI was used to design active filters. Their selectivity, insertion losses and noise analysis is presented and discussed.     

Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters

This work presents a new low-loss active inductor whose self-resonance frequency and quality factor parameters can be adjusted independently from each other. In order to achieve this property, a new input topology has been employed which consists of cascode structure with a diode connected transistor. Furthermore, the proposed input topology makes the device robust in terms of its performance over variation in process, voltage and temperature. Additionally, RC feedback is used to cancel series-loss resistance of the active inductor, which allows self-resonant enhancement as well. Schematic and post-layout simulation results show the theoretical validity of the design. To validate the design feasibility for process, voltage and temperature changes, Monte Carlo and temperature analysis are done. Suggested structure shows inductor behavior in the frequency range of 0.3–11.3 GHz. Maximum quality factor is obtained as high as 2.1k at 5.9 GHz. Total power consumption is as low as 1 mW with 1.8 V power supply.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

宽阻带超宽带带通滤波器的设计

针对某些传统滤波器阻带较窄,抑制谐波性能差的缺点,对传统的阶梯阻抗谐振器( SIR)进行了改进,使之通带内回波损耗降低,频带增宽,同时利用缺陷接地结构(DGS)制谐波特性来增加阻带宽度,得到一款低插损滤波器,最后使用HFSS建模仿真.结果表明:该滤波器具有良好的通带效果,通带内插入损耗小于l dB,回波损耗大于10 d...     

一种Butterworth带通滤波器的设计与实现

提出一种基于MAX260的Butterworth带通滤波器设计方法.介绍了设计Butterworth滤波器的基本原理,以及利用MAX260实现该种滤波方式的具体过程.在实验室环境下举出具体实例实现了四阶Butterworth带通滤波器,并验证了其滤波性能.测试结果表明该方法具有较好的滤波效果.由于该方法中信号滤波由有源程控滤波器芯片完成,可降低微控制器的运算负担,有利于提升系统性能.     

Novel micromachined lumped band pass filter for 5.2 GHz WLAN applications

This paper describes the design, manufacturing and experiments of a lumped element band pass filter in a new topology. The design starts from a second order capacitive coupled resonator topology. An additional series inductor is inserted in the filter classical topology, for shifting two transmission zeros on the real frequency axes in the filter's band stop, to improve the high frequency response. Design equations for the new band stop resonance frequency are presented together with the analysis of the correspondence between the band pass and band stop attenuation vs. the quality factor of the shunt and series inductors used. The filter is supported on a 6.4 μm thin dielectric membrane, and is manufactured using silicon micromachining, in CPW technology. Measurements illustrated a minimum 2.75 dB insertion loss at 5.5 GHz in the band pass, and more than 40 dB attenuation, at 8 GHz.     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

CMOS RF class-D power amplifier with bandpass sigma-delta modulation

A CMOS radio frequency class-D amplifier is analysed and simulated with a bandpass ΣΔ modulated drive signal. The design includes a five stage driver and operates from 3.3 V. The simulated power efficiency at 181 MHz is 40.1% for a two tone source, and 16.6% for a 8.7 dB peak-to-average wideband code-division multiple access source signal. Equations are derived which demonstrate the relationship between amplifier load power, power efficiency, and modulator parameters called coding efficiency and average transition frequency.     

二阶有源低通滤波器设计与仿真研究

介绍了利用子系统的级联、反馈及电路仿真手段设计有源二阶滤波器简便方法。给出了电路参数选取的技巧。对反馈电路的接入点选择;系统传递函数的计算与验证都给出了详细的分析。仿真实验证明,通过调试可变电阻值,可以得到性能优良的二阶滤波器。     

基于LTC1068-200的低频带通滤波器设计

在蓄电池性能监测过程中,接收的信号都是比较微弱的低频信号,而且为了得到更多的信息,往往向蓄电池施加多个频率的激励。因此,设计带通滤波器以提高抗干扰能力,而且中心频率要可调。开关电容滤波器可实现低通、高通、带通和带阻滤波功能,而且中心频率可调节,文中采用了LTC1068-200开关电容滤波器集成模块进行电路设计,时钟频率由CD4046锁相环控制。仿真结果表明本文设计的滤波器通带宽度可以达到5 Hz,中心频率从10 Hz到1 kHz可调节,满足实际需要。     

Design of CMOS VHF/RF Biquadratic Filters

In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G _m-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.     

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602 MHz for DTV programs. In experiments, the polyphase filter can achieve 85 dB for the image rejection in the center frequency. The main signal can be gained about 2-5 dB without using extra amplifier. The chip size is about 0.09 mm², and the average power dissipation is about 15 mW, when the chip technology employed TSMC 0.35 μm CMOS process. The proposed chip outperforms with less area and higher gain.     

SC filter for RF sampling and downconversion with wideband image rejection

In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.     

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve best-in-class HR ratio (HRR) performance. The achieved concurrent 3rd order HRR and 5th order HRR are greater than 80 dB and 70 dB, respectively, after calibration. The even order HRR is also calibrated to greater than 80 dB. A single calibration performed at 750 MHz was further observed to be effective over more than two octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65 nm CMOS technology. Input RF frequency range was 0.15–1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is −7 dBm at a total gain of 48 dB.     

Distributions of results of analysis by means of spectrum analyzer with ideal band pass filter and true integrator

The theoretical model of the probability density functions of results of Gaussian white noise spectrum analysis is constructed and experimentally verified. The analyzer of the ‘filtering-squaring-averaging’ type is assumed with true integrator as the averager and with the ideal filter with very narrow and maximum wide pass band. Simple approximative ways for probability density functions calculation are derived. It is found that these distributions do not coincide with χ²-distributions. Previously derived estimates of the spectrum analysis statistical error are also experimentally verified.     

高可靠性发夹型带通滤波器的设计与制作

依据微带发夹型带通滤波器的原理,进行了数学建模,并结合ADS2008的优化仿真功能对滤波器进行了优化设计。根据仿真结果,在高介电常数的陶瓷基板[MgTiO3-CaTiO3-Nd2O3,εr=18,Q·f=65000(7GHz),板厚度0.8mm]上制作了中心频率f0=3.5GHz、带宽为3.25~3.75GHz的滤波器。经测试发现,制得的滤波器具有良好的端口反射特性,可靠性高,基本满足3.25~3.75GHz频率范围内的特殊通讯要求。这表明本研究所用设计方法合理,适合于工程应用。     

双传输零点LTCC带通滤波器的设计与制作

采用仿真软件Ansoft HFSS,构建了具有双传输零点的LTCC带通滤波器(BPF)的物理模型,即在无传输零点的二阶带通滤波器的基础上并联一个反馈电容来实现双传输零点。根据仿真结果,采用LTCC工艺制作了封装尺寸为1206,具有两个传输零点的片式BPF样品,用矢量网络分析仪Agilent 8722ES进行测试。结果表明:测量结果与仿真数据基本相符,滤波器中心频率为2.7GHz。该滤波器适用于日益小型化的移动通信设备。     

Resistorless first-order all-pass filter with electronic tuning

A first-order all-pass filter (APF) with electronic tuning properties is presented. The filter consists of only active components and a single-grounded capacitor. The circuit is cascadable, has small sensitivities, and suitable for monolithic integration, and it can also operate at high frequencies.