A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power mm-wave digital and RF circuit capability

A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz F/sub t/, 208-GHz F/sub max/, 1.45-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF//spl mu/m/sup 2/, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications.     

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage withpicoampere stand-by current

A super cut-off CMOS (SCCMOS) scheme is proposed and demonstrated by measurement to achieve high-speed and low stand-by current CMOS VLSIs in sub-1-V supply voltage regime. By overdriving the gate of a cut-off MOSFET, the SCCMOS suppresses leakage current below 1 pA per logic gate in a stand-by mode while high-speed operation in an active mode is possible with low-threshold voltage of 0.1-0.2 V. The SCCMOS pushes the low-voltage operation limit 0.2 V further down compared with conventional schemes while maintaining the same stand-by current level     

A 1.3 GHz SOI CMOS test chip for low-power high-speed pulseprocessing

A test chip has been fabricated in a fully depleted SOI CMOS process with 0.25-μm drawn gate length, It successfully demonstrates the types of circuits required to perform digital filtering, detection, and data thinning functions at high clock speeds. The test chip contains over 5000 transistors and was clocked at speeds up to 1.3 GHz. A target application for these circuits is a very wideband compressive receiver for real-time spectral analysis, which requires digital signal processing to be performed on a 20-Gb/s data stream formed by digitizing a stream of fast analog pulses. Adjustable high-speed on-chip clocks, input and output registers, and large decoupling capacitors allowed testing of the chip to be performed using an inexpensive, low-speed probe card and a standard wafer prober     

New device structure using array transistors and flexible U-grooves suitable for 18-V, high-performance SOI complementary bipolar LSIs

We have developed a new device structure suitable for high-performance and high-power mixed signal large scale integrations (LSIs) using 0.35-/spl mu/m SOI complementary bipolar transistors. The new structure is composed of array transistors for various operating currents and flexible U-groove (trench) layout for high-power transistors. Thermal simulation results showed that the thermal resistance could be reduced by 40% by using the flexible U-groove layout. Test structure measurements showed that the maximum operating currents of a double polysilicon self-aligned NPN transistor were improved by 2 and 3.5 times by using ballasting resistors and ballasting resistors with flexible U-groove layout, respectively. The effects of the transistor structure on the thermal resistance and the maximum operating current were discussed.     

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

A 0.9-V 0.5-μA, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode nMOS transistors buffer a bulk-driven pMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low-voltage translinear control circuit     

High performance 3.3- and 5-V 0.5-μm CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-μm CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4     

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.     

A 3-V 0.5-μm CMOS A/D audio processor for a microphone array

A 0.5-μm 3-V CMOS mixed-mode audio processor is presented. It is mainly composed of 11 low-noise input channels and a dedicated digital audio processor. Analog input signals are provided through an 11-microphone array. The chip size is about 50 mm², and the power dissipation is less than 100 mW. This circuit is dedicated to multimedia applications     

BCB-bridged distributed wideband SPST switch using 0.25-/spl mu/m In/sub 0.5/Al/sub 0.5/As--In/sub 0.5/Ga/sub 0.5/As metamorphic HEMTs

In/sub 0.5/Al/sub 0.5/As--In/sub 0.5/Ga/sub 0.5/As metamorphic high-electron mobility transistor (mHEMT) dc-30 GHz distributed single-pole-single through (SPST) switches were designed and fabricated using the low-/spl kappa/ benzocyclobutene (BCB) bridged technology. The current gain cutoff frequency, and the electron transit time of In/sub 0.5/Al/sub 0.5/As--In/sub 0.5/Ga/sub 0.5/As mHEMTs have been investigated. By analyzing the extrinsic total delay time, the effective velocity of electrons can be estimated, and the average velocity is 2.3/spl times/10/sup 7/cm/s. The dc-30 GHz distributed wideband SPST switch exhibits an insertion loss of less than 5.5 dB, and an isolation larger than 30 dB, which is the first demonstration of the high-isolation of InAlAs-InGaAs mHEMTs monolithic switch. As to the power performance, this switch can handle the power up to 12 dBm at 2.4 GHz. After over 250 h of 85-85 (temperature =85/spl deg/C, humidity =85%) environmental evaluation, this BCB passivated and bridged microwave and monolithic integrated circuit switch demonstrates reliable RF characteristics without any significant performance change, which proves that this process using the low-/spl kappa/ BCB layer is attractive for millimeter-wave circuit applications.     

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with acharge-transfer presensing scheme

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V_cc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

A new fabrication technology for AlGaAs/GaAs HEMT LSIs using InGaAsnonalloyed ohmic contacts

The authors studied the nonalloyed ohmic characteristics of HEMTs (high electron mobility transistors). At high integration levels, nonalloyed ohmic contacts were found to have two advantages: an extremely short ohmic length with low parasitic source series resistance and direct connection between the source/drain and gate with the same metal. The propagation delay in a ring oscillator with a single-metal source/drain and gate formed simultaneously was 37 ps/gate (L _g=0.9 μm). The very short ohmic metal contacts and just three contact holes made it possible to reduce the memory cell area greatly. The cell is 21.5×21.5 μm², one of the smallest ever reported for a GaAs-based static RAM. Using smaller load HEMTs or resistor loads in the memory cell, combined with nonalloyed ohmic technology with quarter- or subquarter-micrometer-gate HEMTs it is possible to fabricate a very-high-speed LSI such as a 64-kb static RAM with a reasonable chip size     

A fast measurement technique of MOSFETI/sub d/-V/sub g/ characteristics

In this letter, we developed an improved ultrafast measurement method for threshold voltage V/sub th/ measurement of MOSFETs. We demonstrate I/sub d/--V/sub g/ curve measurement within 1 /spl mu/s to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantitatatively. The ultrafast V/sub th/ measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO/sub 2/ gate dielectric is demonstrated.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

2.5-V bipolar/CMOS circuits for 0.25-μm BiCMOS technology

An ECL circuit with an active pull-down device, operated from a CMOS supply voltage, is described as a high-speed digital circuit for a 0.25-μm BiCMOS technology. A pair of ECL/CMOS level converters with built-in logic capability is presented for effective intermixing of ECL with CMOS circuits. Using a 2.5-V supply and a reduced-swing BiNMOS buffer, the ECL circuit has reduced power dissipation, while still providing good speed. A design example shows the implementation of complex logic by emitter and collector dottings and the selective use of ECL circuits to achieve high performance     

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-μm MTCMOS/SIMOX technology     

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be considered for the low-voltage operation. A hidden error-check-and-correction (HECC) scheme compensated the access time penalty caused by the ECC logic on the output critical path. And a multi-column ECC word assignment (MCE) increased the multi-bit-error immunity while using only 1-bit-correctable ECC which minimized area penalty. A source-level-adjusted direct sense amplifier (SLAD) and a write-replica circuit with an asymmetrical replica memory cell (WRAM) for the device-fluctuation-tolerant access control were also designed. A 130-nm CMOS 32-Kbit SRAM-macro was fabricated with these circuit techniques, which demonstrated: 1) 0.3-V operation with 6.8 MHz; 2) 30-MHz operation which is feasible for mobile use even at 0.4 V, while keeping 960MHz at 1.5 V; and 3) a reduction by 3.6/spl times/10/sup 5/ in soft-error rate compared with that of conventional ECC.     

All-digital low-power CMOS pulse generator for UWB system

An all-digital CMOS ultra-wideband (UWB) pulse generator which complies with FCC regulations is presented. The proposed pulse generator generates a single UWB pulse satisfying FCC regulations without any filtering. The average power consumption of the whole circuit is 15.4 mW and 675 /spl mu/W at the pulse repetition frequency of 500 and 1 MHz, respectively.