Evaluation of 1/f Noise Characteristics for Si‐Based Infrared Detection Materials

Silicon antimony films are studied as resistors for uncooled microbolometers. We present the fabrication of silicon films and their alloy films using sputtering and plasma‐enhanced chemical vapor deposition. The sputtered silicon antimony films show a low 1/f noise level compared to plasma‐enhanced chemical vapor deposition (PECVD)‐deposited amorphous silicon due to their very fine nanostructure. Material parameter K is controlled using the sputtering conditions to obtain a low 1/f noise. The calculation for specific detectivity assuming similar properties of silicon antimony and PECVD amorphous silicon shows that silicon antimony film demonstrates an outstanding value compared with PECVD Si film.     

Characteristics of thin film transistors fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition

Thin-film transistors (TFTs) fabricated in polysilicon films deposited by plasma enhanced chemical vapor deposition (PECVD) were characterized. The transistors were fabricated using a low temperature process (i.e., <- 700° C). The characteristics of the devices were found to improve as the deposition temperature of the polysilicon film increased. The best characteristics (μ _FE of 15 cm²/V _s andV _TH of 2.2V) were measured in the devices fabricated in the film deposited at 700° C. The devices fabricated in the PECVD polysilicon films were compared to those fabricated in polysilicon films deposited by thermal CVD in the same reactor in order to decouple the effect of the plasma. A coplanar electrode structure TFT with adequate characteristics (μ _FE of 8 cm²/V _s) was also demonstrated in the PECVD polysilicon films.     

Ultra Thin Film Encapsulation of Organic Light Emitting Diode on a Plastic Substrate

We have carried out the fabrications of a barrier layer on a polyethersulfon (PES) film and organic light emitting diode (OLED) based on a plastic substrate by means of atomic layer deposition (ALD). Simultaneous deposition of 30 nm AlO_x film on both sides of the PES film gave a water vapor transition rate (WVTR) of 0.062 g/m²/day (@38°C, 100% R.H.). Further, the double layer of 200 nm SiNx film deposited by plasma enhanced chemical vapor deposition (PECVD) and 20 nm AlOx film by ALD resulted in a WVTR value lower than the detection limit of MOCON. We have investigated the OLED encapsulation performance of the double layer using the OLED structure of ITO / MTDATA (20 nm) / NPD (40 nm) / AlQ (60 nm) / LiF (1 nm) / Al (75 nm) on a plastic substrate. The preliminary life time to reach 91% of the initial luminance (1300 cd/m²) was 260 hours for the OLED encapsulated with 100 nm of PECVD‐deposited SiNx and 30 nm of ALD‐deposited AlO_x.     

聚酰亚胺衬底柔性非晶硅薄膜电池集成串联组件的研究

研究了柔性Si基薄膜太阳电池集成串联组件的制备与关键技术。对导电栅线在柔性薄膜太阳电池集成串联组件中的重要性进行了模拟计算,对柔性薄膜太阳电池激光刻蚀进行了理论分析与实验优化,并对柔性Si基薄膜太阳电池集成串联组件进行了设计与研制。在聚酰亚胺(PI)衬底上,通过卷对卷磁控溅射与卷对卷等离子增强化学气相沉积(PECVD)依次沉积复合背反射层Ag/ZnO、Si基薄膜层和透明导电膜层,采用激光刻蚀与丝网印刷工艺相结合实现集成串联,制备了柔性非晶Si(a-Si)薄膜太阳电池集成串联组件。柔性单结集成串联组件有效面积转换效率达到了4.572%(AM0),开路电压Voc=5.065V,填充因子FF=0.552。     

Low temperature Si2H6 Si epitaxy in-situ doped with AsH3/SiH4

The use of disilane (Si₂H₆) as a silicon source for epitaxial deposition was investigated for both very low pressure chemical vapor deposition (thermal CVD) and plasma enhanced chemical vapor deposition (PECVD) from 600 to 800° C. The growth rates observed for temperatures at or below 750° C were at least an order of magnitude higher than those observed for silane (SiH₄) using similar deposition conditions. An argon plasma was used to sputter clean the silicon surface, in-situ, immediately before the deposition. It was found that a low dc bias on the substrate during the argon sputter cleaning process helped remove carbon and oxide from the surface of the silicon substrate. A 16 min Ar sputter clean at 650° C, 2.5 W rf power, and •50 V dc bias resulted in a carbon and oxygen concentration at the epilayer-substrate of less than 4 × 10¹⁸/cm³ and 2 × 10¹⁸/cm³, respectively. In situ arsenic doping during disilane epitaxial growth was carried out by thermal CVD and PECVD using arsine (AsH₃) diluted in silane (SiH₄) at 800° C. The results were compared to similar experiments using only SiH₄ as the silicon source. Up to 500 ppm of arsine was diluted in the reactant gas and it was found that the Si₂H₆ growth rates were insensitive to the arsine concentraton in the gas phase.     

Growth and characterization of PECVD semi-insulating polysilicon films and resistors

Semi-insulating polycrystalline (SIPOS) films deposited by plasma-enhanced chemical vapor deposition (PECVD) were investigated. The films were deposited using monosiane, nitrous oxide and argon at 300° C in a parallel-plate plasma reactor. Rapid thermal annealing was shown to restructure and densify the films with an activation energy of 0.7 eV. Nitrogen was found to be incorporated into the as-deposited films but not in annealed films. It was found that the resistivity of PECVD SIPOS was less sensitive to temperature and an order of magnitude lower than the values reported for LPCVD SI-POS. The differences are thought to be due to the more amorphous nature of PECVD material because of the lower deposition temperature of 300° C. This work was supported by a research contract from Sandia National Laboratories.     

Hydrogen-assisted low-temperature plasma-enhanced chemical vapor deposition of thin film encapsulation layers for top-emission organic light-emitting diodes

In this work, we developed a single high-performance SiN_x encapsulation layer that can be directly integrated into organic devices by low-temperature plasma-enhanced chemical vapor deposition (PECVD). We investigated a hydrogen-assisted low-temperature PECVD process at a temperature of 80 °C. The thin film density improved with an increased hydrogen gas ratio, and the moisture permeability was less than 5 × 10⁻⁵ g/m²·day. To verify the stability of the PECVD process, we applied the SiN_x encapsulation layer directly to top-emitting organic light-emitting diodes. The results showed minor changes in the current-density–voltage characteristics after the PECVD process, as well as high reliability after a water dipping test.     

TEOS-H_2O等离子CVD新技术

介绍了用正硅酸乙酯和水混合物进行等离子体增强化学汽相淀积制备氧化硅膜的原理和工艺, 对膜质量进行了分析和讨论     

Low-temperature and low thermal budget fabrication ofpolycrystalline silicon thin-film transistors

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (⩽550°C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH₃ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm²/V-s, ON/OFF current ratio of over 10⁷, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate     

Annealing effects in the PECVD SiO2 thin films deposited using TEOS, Ar and O2 mixture

In this work, we present the results obtained on the characterization of silicon oxide thin films deposited by plasma enhanced chemical vapor deposition (PECVD) using a mixture of tetraethylorthosilicate (TEOS), oxygen and argon. The electrical characteristics of the implemented MOS capacitors, after the annealing process (600°C), showed an increase in the break-down strength as well as the effective charge density.     

Simulation of elevated temperature aluminum metallization usingSIMBAD

A ballistic deposition model, SIMBAD, has been extended to simulate physical vapor deposition onto substrates at elevated temperatures. The model has been expanded to account for the effect of film curvature on surface diffusion. The effects on via coverage and filling have been simulated for aluminum films, and complete planarization of a 1:1 aspect ratio via is predicted for a temperature of 550°C. Via aspect ratio and sidewall taper can also strongly affect coverage and filling. Biased sputtering has also been incorporated into the model and shows that a primary effect is a substantial reduction in the temperature required to achieve full planarization. However, void formation and substrate damage are problems predicted to occur under some bias sputter conditions     

A planarized SiO2interlayer dielectric with bias-CVD

A Bias-CVD^TMprocess has been developed for depositing planarized silicon dioxide films. The process uses, in addition to PECVD deposition, an argon ion etch for planarization. A distinguishing feature of this process is the use of a unique sequence of depositions and etching to control contour and topography, eliminate keyholing, and reduce pinhole density. By varying this Sequence, the film topography can range from conformal to fully planarized. A cold-wall low-pressure CVD system with an eight-wafer batch and 13.56-MHz RF capability was used in this study. Because of the chamber geometry, a dc bias is induced in the wafer support during the RF plasma processing. This bias, typically a few hundred volts, provides the accelerating field for the ion etching of the film. It is the anisotropy of this etch that makes planarization possible. The film has the density and index of refraction of thermally grown oxide. The Si to O ratio is 1 to 1.9 with 8-percent nitrogen and 0.1-percent argon, by RBS. SIMS analysis shows no trace of heavy metals. The effect of process parameters has been characterized. Dynamic RAM's deposited with the sloped film show normal yield and electrical properties; there is no evidence of radiation damage.     

Gate oxide reliability concerns in gate-metal sputtering deposition process: an effect of low-energy large-mass ion bombardment

The effects of ion species/ion bombardment energy in sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputtering deposition for gate electrode formation makes it possible to minimize the plasma-induced gate oxide damage. The Xe plasma process exhibits 1.5 times higher breakdown field and five times higher 50%-charge-to-breakdown (Q_BD). In the gate-metal sputtering deposition process, the physical bombardment of energetic ion causes to generate hole traps in gate oxide, resulting in the lower gate oxide reliability. The simplified model providing a better understanding of the empirical relation between the gate oxide damage and the ion-bombardment energy to gate oxide in gate-metal sputtering deposition process is also presented.     

High‐quality surface passivation of silicon solar cells in an industrial‐type inline plasma silicon nitride deposition system

We have studied the surface passivation of silicon by deposition of silicon nitride (SiN) in an industrial‐type inline plasma‐enhanced chemical vapor deposition (PECVD) reactor designed for the continuous coating of silicon solar cells with high throughput. An optimization study for the passivation of low‐resistivity p‐type silicon has been performed exploring the dependence of the film quality on key deposition parameters of the system. With the optimized films, excellent passivation properties have been obtained, both on undiffused p‐type silicon and on phosphorus‐diffused n⁺ emitters. Using a simple design, solar cells with conversion efficiencies above 20% have been fabricated to prove the efficacy of the inline PECVD SiN. The passivation properties of the films are on a par with those of high‐quality films prepared in small‐area laboratory PECVD reactors. Copyright © 2004 John Wiley & Sons, Ltd.     

用PECVD制备掺氟氧化硅低介电常数薄膜

用ＰＥＣＶＤ淀积了低介电常数的掺氟氧化硅介质薄膜,ＳｉＦ４的流量达到６０ｓｃｃｍ时,薄膜的相对介电常数可以降低到３．２。对试样的ＦＴＩＲ分析表明,薄膜中大部分的氟以Ｓｉ－Ｆ键形式存在。Ｃ－Ｖ特性测试表明,薄膜介电常数随氟含量的增加而减小,但薄膜的吸水性随氟含量的增加而变大。并进一步讨论了介电常数和薄膜稳定性与薄膜中氟原子含量之间的内在联系。     

沉积功率和气压对低频氮化硅薄膜应力的影响

利用等离子体增强化学气相沉积(PECVD)工艺,在不同射频功率,不同反应气压条件下制备了氮化硅薄膜。研究了低频工艺中氮化硅薄膜的沉积速率、应力以及厚度均匀性与其二者的关系。结果表明,射频功率的改变直接影响到离子对衬底的轰击效应,而反应气压的改变影响气体分子的平均自由程。离子轰击效应和分子平均自由程对氮化硅薄膜的生长过程产生影响,从而影响沉积速率、应力以及厚度均匀性等基本性质。     

纳米硅薄膜与纳米电子学

纳米半导体硅薄膜是利用等离子体增强化学气相沉积（ＰＥＣＶＤ）方法制备的,制备可以很好地进行调节控制。纳米硅薄膜由两种组元：纳米尺度晶粒组元和晶粒间的界面组元,即晶态相和晶界相组成。纳米半导体硅薄膜对发展半导体器件,例如量子功能器件和薄膜敏感器件等,很有价值。     

氧化锌薄膜的研究与开发进展

阐述了ＺｎＯ薄膜材料的结构特点，电学性质和光学特性。分析了薄膜研制、应用与开发现状，展望了产业化发展前景。     

Optimization of saturation current density of PECVD SiN coated phosphorus diffused emitters using neural network modeling

Emitter surface passivation by low temperature plasma enhanced chemical vapor deposition (PECVD) silicon nitride is investigated and optimized in this paper. We have found that the saturation current density of a 90±10 μ/sq phosphorus diffused emitter with N_s ≈3 x 10¹⁹ and X_j ≈0.3 μm can be lowered by a factor of eight by appropriate PECVD silicon nitride deposition and photoassisted anneal. PECVD silicon nitride deposition alone reduces the emitter saturation density (J_oe) by about a factor of two to three, and a subsequent photoanneal at temperatures ≥350°C reduces J_oe by another factor of three. In spite of the larger flat band shift for direct PECVD silicon nitride coating, the silicon nitride induced surface passivation is found to be about a factor of two inferior to the thermal oxide plus PECVD silicon nitride passivation due to higher interface state density at the SiN/SiO₂ interface compared to SiO₂/Si interface. A combination of statistical experimental design and neural network modeling is used to show quantitatively that lower radio frequency power, higher substrate temperature, and higher reactor pressure during the PECVD deposition can reduce the J_oe of the silicon nitride coated emitter.     

>16% thin‐film epitaxial silicon solar cells on 70‐cm2 area with 30‐µm active layer,porous silicon back reflector,and Cu‐based top‐contact metallization

We demonstrate the use of a copper‐based metallization scheme for the specific application of thin‐film epitaxial silicon wafer equivalent (EpiWE) solar cells with rear chemical vapor deposition emitter and conventional POCl₃ emitter. Thin‐film epitaxial silicon wafer equivalent cells are consisting of high‐quality epitaxial active layer of only 30 µm, beneath which a highly reflective porous silicon multilayer stack is embedded. By combining Cu‐plating metallization and narrow finger lines with an epitaxial cell architecture including the porous silicon reflector, a J_sc exceeding 32 mA/cm² was achieved. We report on reproducible cell efficiencies of >16% on >70‐cm² cells with rear epitaxial chemical vapor deposition emitters and Cu contacts. Copyright © 2011 John Wiley & Sons, Ltd.