Second generation fully differential current conveyor based analog circuits

In this paper, we present a new voltage-mode biquad filter that uses a six-terminal CMOS fully differential current conveyor(FDCCII). The FDCCII with only 23 transistors in its structure and operating at ± 1.5 V, is based on a class AB fully differential buffer. The proposed filter has the facility to tune gain, ωo and Q. A circuit division circuit(CDC) is employed to digitally control the FDCCII block. This digitally controlled FDCCII is used to realize a new reconfigurable fully-differential integrator and differentiator. We performed SPICE simulations to determine the performance of all circuits using CMOS 0.25 μm technology.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Adaptive CMOS analog circuits for 4G mobile terminals—Review and state-of-the-art survey

The fourth-generation (4G) of cellular terminals will integrate the services provided by previous generations second-generation/third-generation (2G/3G) with other applications like global positioning system (GPS), digital video broadcasting (DVB) and wireless networks, covering metropolitan (IEEE 802.16), local (IEEE 802.11) and personal (IEEE 802.15) areas. This new generation of hand-held wireless devices, also named always-best-connected systems, will require low-power and low-cost multi-standard chips, capable of operating over different co-existing communication protocols, signal conditions, battery status, etc. Moreover, the efficient implementation of these chipsets will demand for reconfigurable radio frequency (RF) and mixed-signal circuits that can adapt to the large number of specifications with minimum power dissipation at the lowest cost.Nanometer CMOS processes are expected to be the base technologies to develop 4G systems, assuring mass production at low cost through increased integration levels and extensive use of digital signal processing. However, the integration in standard CMOS of increasingly complex analog/RF parts imposes a number of challenges and trade-offs that make their design critical.These challenges are addressed in this paper through a comprehensive revision of the state-of-the-art on transceiver architectures, building blocks and design trade-offs of reconfigurable and adaptive CMOS RF and mixed-signal circuits for emerging 4G systems.     

应用于心电采集系统的低谐波失真全差分VGA测试验证

本文通过理论分析和流片测试验证了一个应用于心电采集系统的具有较低总谐波失真(THD)的全差分VGA。该VGA采用电容反馈技术来降低系统的非线性。本系统基于SMIC 0.18-μm CMOS工艺进行设计和流片,芯片面积仅为0.11 mm2。芯片测量结果同电路后仿真结果相吻合。测试结果表明VGA以3dB的增益步长由6.17dB到43.75dB变化,其高通角频率和低通角频率分别为0.22Hz和7.9kHz;各个增益级下获得最大的THD为-59.4dB。表明了该全差分VGA具有低的THD,其主要性能指标均满足心电采集系统在UWB健康监护与遥测系统中的应用要求。     

基于SLPS的模拟电路故障样本自动获取技术

故障样本数据的获取是模拟电路故障诊断中最基本的步骤。为了实现短时间内多次进行故障注入、获取大量样本数据,提出了基于SLPS的样本数据自动获取技术。利用SLPS将PSpice与Matlab结合,采用Matlab编程,实现故障模拟电路仿真数据获取的自动化。实际应用表明该方法操作简便,自动化程度高。     

On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis

A method is proposed to obtain a minimal set of test nodes of an analog circuit for isolating all faulty conditions in the fault dictionary approach. Relevant theorem along with the proof is also given. Proposed method is extremely fast. This method is illustrated with an active filter circuit example.     

A new high-performance CMOS fully differential second-generation current conveyor with application example of biquad filter realisation

In this article, a new complementary metal oxide semiconductor (CMOS) high-performance fully differential second-generation current conveyor (FDCCII) implementation is proposed. The presented FDCCII provides high-output impedance at terminals Z+ and Z?, good linearity and excellent output–input current gain accuracy. Also, the proposed FDCCII circuit operates at a supply voltage of ±1.3 V. The applications of the FDCCII to realise voltage-mode multifunction filters are given. Simulations are performed using TSMC CMOS 0.35-μm technology to verify theoretical results.     

A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations

In this paper we present a new current-mode basic building block that we named voltage and current gained second generation current conveyor (VCG-CCII). The proposed active block allows to control and tune both the CCII current gain and the voltage gain through external control voltages. It has been designed, at transistor level in a standard CMOS technology (AMS 0.35 μm), with a low single supply voltage (2 V), as a fully differential active block. The proposed integrated solution, having both low-voltage (LV) and low-power (LP) characteristics, can be applied with success in suitable IC applications such as floating capacitance multipliers and floating inductance simulators, utilizing a minimum number of active components (one and two, respectively). Simulation results, related to floating impedance simulators, are in good agreement with the theoretical expectations.     

A low flicker noise direct conversion receiver for IEEE 802.11g wireless LAN using differential active inductor

In this paper, a low flicker-noise, 2.4 GHz direct onversion receiver (DCR) has been designed. A dynamic current injection (DCI) technique has been utilized in addition with a tuning inductor in the mixing stage. The tuning inductor has been replaced by a differential active inductor circuit, which gives the same inductance, with less chip size and high quality factor. The DCR has been designed in a TSMC 0.18 μm 1P6M CMOS process for wireless LAN 802.11g applications. The proposed DCR achieves 6.7 dB SSB-NF, 34 dB conversion gain, −13.5 dBm IIP3, and flicker noise (1/f) corner frequency of 30 kHz with 137.5 mW power consumption from 1.8 V supply voltage.     

用于晶体振荡器温度补偿的次方电压产生方法

为了获得更高精度的时钟源,需要对晶体振荡器进行温度补偿以便减小频率随温度的变化。对比晶体振荡器不同的温度补偿方式,模拟温度补偿具有较高的性能,而模拟温度补偿电路的主要模块就是获取与温度成次方关系的补偿电压。文中采用了一种模拟乘法器的方法来获得与温度成不同指数关系的电压,在全差分放大器的输入端接入4个MOS管,利用其工作于线性区时的电流电压关系并结合全差分放大器来实现两个模拟量之间的相乘,进而获得与温度成1次方、2次方、3次方、4次方和5次方关系的补偿电压。获得的这些电压通过加和电路叠加后即可用于晶体振荡器的高阶温度补偿。通过仿真,得到全差分放大器的差模增益为78.6 dB,乘法器可以实现两个信号的相乘,且应用该方法进行补偿的晶体振荡器的频率偏移为±2 ppm。     

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.