G729 Voice Decoder Design

Embedded digital signal processing (DSP) systems are usually associated with real time constraints and/or high data rates such that fully software implementations are often not satisfactory. In that case, mixed hardware/software implementations are to be investigated. This paper presents the design of a HW/SW G.729 voice decoder dedicated to embedded systems. The decoder has been built around, on the one hand a reconfigurable digital circuit (FPGA) to achieve the so called IP hardware part—the autocorrelation computation—using a linear systolic array, and on the other hand a digital signal processor (DSP) for the remainder of the algorithm. Apart such an implementation is typically driven by the use of reusable component (IP) it is of great interest for new G729-based applications such as Voice over IP (VoIP) for example. It results in an overall reduction of the execution time per frame. Another interesting point is the design of a parameterizable autocorrelation block which can be useful for a wide range of applications such as GSM 13 Kbit/s, APC 9.6 Kbit/s and G723 6.3 Kbit/s and 5.3 Kbit/s. In the G729 context and using a V50 Virtex FPGA, the execution time of this function is 10 times faster than a TMS320C6201 DSP implementation. Fatma Sayadi is Ph.D. student at Faculty of Sciences, Monastir, Tunisia in collaboration with the LESTER Laboratory, University de Bretagne Sud, Lorient, France. She is a member of Laboratory of Electronics and Micro-Electronics. His researches interest, the implementation of Digital Signal, high level design using VHDL language, Hardware/Software Co-design. Emmanuel Casseau received his Ph.D Degree in Electrical Engineering in 1994. He is currently an Associate Professor in the Electronic Department at the University de Bretagne Sud, Lorient, France. He is also in charge of the IP project of the Lester Lab., University de Bretagne Sud. His research interests include system design, high-level synthesis, virtual components and SoCs. Mohamed Atri born in 1971, received his Ph.D. Degree in Micro-electronics from the Science Faculty of Monastir in 2001. He is currently a member of the Laboratory of Electronics & Micro-electronics. His research includes Circuit and System Design, Network Communication, IPs and SoCs. Mehrez Marzougui received the B.Sc. degree from University of Science and Technology (electronic option), Monastir, Tunisia, and the M.Sc. degree in electronic from the same university in 1996 and 1998 respectively. Since 1998, he has been a Ph.D. candidate in Electronic and Micro-electronic laboratory at the University of Sciences and Technology, Monastir, Tunisia. His research interests include hardware/software co-verification and high-level synthesis. Rached Tourki was born in 1948. He received the B.S. degree in Physics (Electronics option) from Tunis University, in 1970; the M.S. and the Doctorat de 3eme cycle in Electronics from Institut d'Electronique d'Orsay, Paris-south University in 1971 and 1973 respectively. From 1973 to 1974 he served as microelectronics engineer in Thomson-CSF. He received the Doctorat d'etat in Physics from Nice University in 1979. Since this date he has been professor in Microelectronics and Microprocessors with the physics department, Faculte des Sciences de Monastir. Eric Martin born in 1961, is a Full Professor at the University of South Brittany in Lorient, France. His interest includes the implementation of Digital Signal and Image Processing and high-level design methods for dedicated circuits.     

G.729语音编码标准及其应用

介绍了G.729协议编码器、译码器原理及应用，并讨论了此协议降低码速率的几个关键技术。     

基于G．729标准的通用IP语音邮件系统

为了将IP网络电话、语音电子商务等通信方式的优点融入电子邮件系统之中，构造大容量，具备电话和电脑两类用户、能随时随地接入的邮件系统。以通用SMTP／POP3邮件协议为基础，提出基于实时语音压缩的IP语音邮件的SMTP／POP3修改协议，并用VC＋＋编程语言实现基于G．729实时语音压缩标准的、具有简单和方便操作界面、具备说话人特征的IP语音邮件系统。系统测试结果表明，系统能够自由实现电脑用户到电话用户、电脑用户到电脑用户、电话用户到电话用户以及电话用户到电脑用户问的语音邮件发送和接收，提供特快语音邮件和普通语音邮件服务功能。     

基于G.729算法的语音处理系统设计

介绍了G.729算法的编解码原理,详细说明了在PXA255平台上使用WM9705音频编解码芯片构建语音采集与处理系统的软硬件方案,并利用INTELIPP多媒体库实现G.729编解码程序。     

iPhone语音通话中G.729A算法的优化及实现

由于G.729A运算模块中开环基音搜索占据了比较大的运算量,在分析了它的算法结构之后,提出了4∶1的抽取方法,即对采样信号点及最佳延时搜索点进行4∶1的抽取。同时,在C代码的基础上去除了串行化模块中1 bit向Word16的数据转换,避免了程序中语音数据的类型转换。最后,将优化后的G.729A封装成静态库,加载到iPhone语音通话软件中进行测试。结果显示,提出的方法降低了开环基音搜索的复杂度,在语音质量稍微有所下降的基础上,提高了语音实时性。     

针对无线语音通信的G.729算法的改进及DSP实现

无线语音通信系统中,由于开放空间的信道衰落特性,使得语音信号在空间传输中受到较大的干扰。针对这一特点,提出了一种基于G.729协议的优化算法。该优化算法粗化了码本搜索,并通过定点溢出保护的去除和宏定义的使用改进了程序运行效率,和原算法相比有较低的计算复杂度和处理延时,利于无线语音的传输。通过DSP硬件仿真实验和人耳听觉辨别表明,在计算复杂度大幅下降的情况下,合成话音质量仍能达到令人满意的效果。     

一种G.729ab和G.723.1联合多通道声码器设计

以TMS320C6203为硬件平台,设计了一种高效率的G.729ab和G.723.1联合多通道声码器.该声码器的不同通道可同时实现G.729ab和G.723.1两种语音压缩算法.通过使用纯汇编指令与C语言结合优化编程,提高核心编解码算法效率,可实时最大支持31个话路语音的G.729ab编解码,或22个话路语音的G.723.1编解码.利用TMS320C6203在片外设McBSP提供声码器连接PSFN的标准E1接口;利用TMS320C6203的HPI接口提供声码器和连接数据网的RTP协议接口,使该联合声码器可灵活应用于媒体网关.     

基于多处理器结构的多路话音编解码器设计

话音业务是卫星通信中的重要业务,设计了一种采用多处理器结构的多路话音编解码器,利用多个处理器协作处理,可以实现卫通网中多路话音通信的信令交互以及数据的压缩处理,并通过主机接口(HOST PORT ITERFACE,HPI)和地址/数据(A/D)总线接口解决了多处理器间的数据交互问题。测试结果表明,该方案设计合理,满足系统使用需求。     

基于DSP平台及G.729A算法的系统设计

应用TMS320VC5509A芯片,通过硬件和软件的设计与调试,实现了对G.729A标准的实时编解码,并应用最新的语音芯片TLV320AIC32,通过和5509A的无缝连接,简化了硬件设计,方便了软件的定点实现。     

基于DSP的G.729语音编解码器设计

设计了基于DSP的G.729语音编解码器,并针对G.729算法标准源码代码效率低、执行时间长的不足,从算法精简、代码优化等方面进行了优化。优化后的算法在保证了高质量语音输出的同时,提高了编码效率,实现了对语音信号的实时处理。最后对系统性能进行了测试,结果满足设计要求。     

基于DSP的G．729语音编解码器的设计

文章介绍了DSP芯片TMS32 0LC549的主要性能 ,并以它为核心实时实现了G .72 9语音编解码器的设计 ,试验证明了这种方案的可靠性     

基于SOC FPGA的PHY设备接口设计及实现

SOCFPGA是一种新兴的芯片设计方案,文章设计了一种基于ALTERA公司SOC FPGA的PHY设备接口设计方案,其中PHY芯片采用marvell公司的88E1111。针对该设计研究了PHY设备在preloader阶段和内核启动阶段的驱动实现。     

数字信号处理器第五讲G.729A语音编码TMS320VC5416 DSP实时实现

IC技术讲座是本刊2005年全新推出的技术类栏目。为了让工程师在设计开发中完善和拓展基础理论与系统知识，丰富应用经验，《世界电子元器件》和中电网联合清华大学等知名院校共同创办了这个栏目，特约知名学者、教授以及著名半导体公司的应用工程师撰写，以系列讲座的方式对热点IC技术进行全面而系统的介绍，涵盖最新技术要点。最先开设的讲座将围绕三大课题：DSP、FPGA和嵌入式系统，每个课题都将连载6期。     

第五讲 G.729A语音编码TMS320VC5416 DSP实时实现(下)

ITU-T G.729 8kb/sCS-ACELP简介 国际电信联盟(ITU-T)于1995年11月正式通过了G.729.ITU-T建议G.729也被称作"共轭结构代数码本激励线生预测编码方案"(CS-ACELP),它是当前较新的一种语音压缩标准.96年ITU-T又制定了G.729的简化方案G.729A,主要降低了计算的复杂度以便于实时实现,因此目前使用的都是G.729A.     

基于G.729A和G.729D的宽带语音编码实现

根据7kHz声频编码标准G.722,采用正交镜像滤波器(Quadrature Mirror Fihers,QMF)法将宽带语音划分为等频带的子带,而后采用高质量的语音编码标准G．729,对低频带使用简化的G．729A,高频带使用较低比特的G．729D,实现了低时延的14．4Kb／s的宽带语音编码。     

高速G.729ab声码器设计及其在媒体网关中的应用

以TMS320C6203为硬件平台,设计了高速G.729ab多通道声码器。使用纯汇编指令与C语言结合优化编程提高核心编解码算法效率,实时支持最大31个话路语音的G.729ab编解码。利用TMS320C6203的在片外设McBSP提供声码器连接PSTN的标准E1接口,设计了用于分组数据收发的RTP协议接口,利用TMS320C6203的HPI接口方式与上层处理器连接,使得声码器可灵活地应用于媒体网关。     

基于DM642的G.729A语音解码系统的设计实现与优化

设计实现了基于DM642的G.729A语音解码系统,着重利用存储器系统优化、软件流水优化、线性汇编优化和内联函数优化降低了代码的运算复杂度并减小系统延迟,提高语音解码系统的整体性能.经测评,优化后的解码器能够实现多媒体语音和数据的同步实时传输.     

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm² by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.     

G·729在PNX1500 DSP平台上的优化设计

文章简单介绍了PNX1500 DSP[1]的体系架构,阐述了基于此架构的语音压缩算法G.729[2]的优化方法。在分析了影响G.729音频编码效率的关键因素基础上,选择了有针对性的优化策略对G.729音频编解码器的Cache部分进行指令优化和算法优化,有效地克服了影响编码速度的瓶颈,改善了编码器效率。