A Low Complexity Algorithm for Generating Turbo Code s-Random Interleavers

In this paper we present a low complexity algorithm based on the bubble search sorting method that can be used to generate Turbo code interleavers that fulfill several criteria like spreading (s-randomness), code matched criteria and even the odd–even property for Turbo Trellis Coded Modulation. Simulation results show that for \(s < \sqrt{N/2}\) the algorithm is extremely efficient for short to medium interleaver lengths.     

Turbo码随机性交织器设计

深空测控中为获得较高的编码增益需要用到信道编译码技术。Turbo码是一种逼近香农限的高性能的信道编译码,其中,交织器的设计是影响Turbo码性能的关键因素之一。论述了交织器设计的基本准则,并详细介绍了3种常见的随机性交织器:伪随机交织器、S随机交织器和S改进型交织器的交织原理,对比分析了3种交织器的优缺点并给出了仿真结果。结果表明,交织器生成方式的不同将带来不同的Turbo码译码性能。     

Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, UMTS turbo decoder. The prototype was designed and fabricated in a 0.35$mu$m CMOS technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast BER simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UMTS defined in the 3GPP standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.     

Turbo码系统中交织器的设计

Ｔｕｒｂｏ码由于很好地应用了香农信道编码定理中的随机性编译码条件而获得了几乎接近香农理论发的性能。其中编、译码过程中交织器的设计是实现随机性的核心。本文主要介绍了分块交织器和伪随机交织器的设计,并提出一种两者相结合的新的交织器类型。根据仿真结果,从理论上分析了三种交织的优缺点及在不同通信领域中应用Ｔｕｒｂｏ码时选取交织器的原则。     

一种周期螺栓交织器的设计

该文分析了对Turbo编码器性能影响的因素,在螺栓交织器的基础上提出了一种周期螺栓交织器,该交织器能使得可分序列变为不可分序列,增加了编码输出序列的重量。仿真结果表明,该交织器具有较优越的性能。     

设计低资源需求的短帧Turbo码交织器

本文叙述在Ｔｕｒｂｏ码交织器中低资源需求的问题,讨论了低资源需求交织器的设计原则,分析了采用所设计交织器的距离谱和误码率特性,报告了在ＦＰＧＡ上综合布线的结果,结果表明该交织器性能较好,易于在专用集成电路上实现。     

光传输系统中一种分组Turbo码的新颖译码算法分析

基于遗传算法与Chase译码算法的各自优势,提出了一种降低运算复杂度并加快译码速度的新颖分组Turbo码(BTC)译码算法.与传统的Chase译码算法相比,该译码算法降低了译码复杂度且加快了译码速度.仿真分析表明,该算法较传统的Chase译码算法在误码率为10-6时提高了约1.15 dB的净编码增益(NCG),具有良好的纠错性能.因而它是一种适用于光传输系统且实用性较强的新颖BTC译码算法.     

Recent Advances in Turbo Code Design and Theory

The discovery of turbo codes and the subsequent rediscovery of low-density parity-check (LDPC) codes represent major milestones in the field of channel coding. Recent advances in the design and theory of turbo codes and their relationship to LDPC codes are discussed. Several new interleaver designs for turbo codes are presented which illustrate the important role that the interleaver plays in these codes. The relationship between turbo codes and LDPC codes is explored via an explicit formulation of the parity-check matrix of a turbo code, and simulation results are given for sum product decoding of a turbo code.     

Turbo码技术的发展

本文对Turbo码技术的历史、现状与未来进行了系统地阐述.Turbo码是20世纪90年代提出的一种前向纠错的信道编码技术.目前Turbo码已发展成为信道编码中最重要的支撑技术文中简介了Turbo码的编解码的基本原理、改进的模型和算法以及目前存在的问题.对未来的重要研究方向也进行了展望.     

The Effect of Block Interleaving in an LDPC‐Turbo Concatenated Code

The effect of block interleaving in a low density parity check (LDPC)‐turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed‐Solomon (RS) code. Thus, an LDPC‐turbo concatenated code can show better performance than the conventional RS‐turbo concatenated code. Furthermore, the performance of an LDPC‐turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.     

码率可配置Turbo译码器设计与实现

本文介绍了码率可配置 Turbo 译码器的 FPGA 设计与实现。可配置 Turbo 译码器可灵活支持 1/3、1/6、1/10 三种码率,减少了器件使用规模和资源,并支持固定迭代次数译码和动态迭代译码。码率可配置 Turbo 译码器最终在 Xilinx 公司的 XC7K325T-2FFG900I 芯片上实现。     

V-BLAST与Turbo码结合的系统性能研究

该文通过仿真研究了V-BLAST与Turbo码结合的系统性能。已有的V-BLAST处理算法与Turbo码的解码是分别进行的,这样在接收端Turbo码的译码器没有充分利用接收信号的软信息。通过将V-BLAST与Turbo码译码有机地结合起来,实现并不复杂,但性能却有明显的提高。     

Design of Rate-Compatible Irregular Repeat Accumulate Codes

We consider the design of efficient rate-compatible (RC) irregular repeat accumulate (IRA) codes over a wide code rate range. The goal is to provide a family of RC codes to achieve high throughput in hybrid automatic repeat request (ARQ) scheme for high-speed data packet wireless systems. As a subclass of low-density parity-check codes, IRA codes have an extremely simple encoder and a low-complexity decoder while providing capacity approaching performance. We focus on a hybrid design method which employs both puncturing and extending. We propose a simple puncturing method based on minimizing the maximal recoverable step of the punctured nodes. We also propose a new extending scheme for IRA codes by introducing the degree-1 parity bits for the lower rate codes and obtaining the optimal proportions of extended nodes through density evolution analysis. The throughput performance of the designed RC-IRA codes in hybrid ARQ is evaluated for both AWGN and block fading channels. Simulation results demonstrate that our designed RC codes offer good error correction performance over a wide rate range and provide high throughput, especially in the high and low signal-to-noise ratio regions.     

光通信中基于分组Turbo码的一种改进Chase译码算法

为了适应光通信发展的要求,依据分组Turbo码(BTC)传统Chase译码算法的分析,提出了一种基于不对等可靠位数的改进新译码算法。使用该算法在每次迭代时将产生一个可靠度参数对外部信息进行修正,从而提高BTC的译码性能。仿真结果表明:在误码率(BER)为10-5且迭代4次的情况下,新BTC译码算法与传统Chase译码算法相比,其净编码增益(NCG)提高了0.9dB,并且在最差情况下给系统增加的译码复杂度都不大。     

一种Turbo码的编码算法仿真实现

对Turbo码的编码的基本原理及编码中的关键元件和技术做了介绍,其中包括交织器的原理,最主要的是对Turbo码在CDMA2000中的编码进行了Matlab仿真,在Turbo码编码的设计仿真过程中对交织器和抽取器进行了算法的实现,模块的封装,计算结果与理论值较接近,有助于对Turbo码的进一步研究.     

Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code

As NAND flash memory fabrication technology scales down to 20 nm and below, the raw bit error rate increases very rapidly and conventional hard-decision based error correction does not provide enough protection. The turbo product code (TPC) based error correction with multi-precision output from NAND flash memory is promising because of high error-correcting performance and flexibility in code construction. In this work, we construct a rate-0.907 (36116, 32768) extended TPC for 2-bit MLC NAND flash memory, and apply the Chase–Pyndiah decoding algorithm. An efficient complexity reduction scheme is also proposed to eliminate redundant computations in the Chase–Pyndiah decoding algorithm. The replica parallel decoding is also employed to lower the error floor. The experimental results that include the effects of flash memory output precision are presented for a simulated flash memory channel.     

Turbo码技术最新进展

Turbo码是信道编码技术的重大突破，结合最新的研究成果，根据Turbo码的结构和实现，系统地分析了其研究和实现中的关键技术，重点分析了Turbo码和其它纠错码的级联，以及和TCM，空时码等技术的结合，及其在均衡和多用户检测技术中的应用。Turbo码已经从理论研究和仿真实验开始走向实际应用，最后叙述了Turbo码在实际系统中的应用进展。     

Turbo码的研究及仿真

介绍了Turbo码的编码译码原理,并研究了影响其性能的各个重要参数,如分量码、帧长、迭代次数、码率及译码算法等,通过Matlab进行软件仿真,对仿真结果进行了详细的分析。仿真的结果表明,在信噪比相同的情况下,交织的长度越大,迭代的次数越多,译码的算法越优,Turbo码性能就越好,但是实现需要的硬件资源也越多,整个系统就会变得很复杂。因此,实际应用中应根据不同的系统需要,再设置相应的参数。     

码率自适应的多维Turbo乘积码系统设计

对多维Turbo乘积码在码率、码型、维数各不相同的情况下的性能进行了仿真研究,得出结论:在相同码率的前提下,选择性能优良的码型,增加码的维数,都可以提高码的性能;并在此基础上提出了一种新型的针对无线信道的码率自适应系统;仿真结果显示,在误码率为10-5时,该系统与固定码率系统相比,在信息传输速率上有明显的优势。