Challenges in analog and mixed-signal fault models

The design and testing of mixed-signal integrated circuits have enjoyed a renaissance in recent years. As is customary with past developments, however, design outpaces testing, and the drive to integrate analog and digital circuits on the same chip exacerbates the test problems. This article reviews the recent results in analog fault modeling-a critical area of mixed-signal testing-and describes the coming challenges for both industrial and university researchers     

一种模数混合电路故障诊断新方法

把模拟电路故障诊断的子网络撕裂诊断法与数字电路故障诊断的伪穷举测试法相结合．提出了一种应用于模数混合电路的故障诊断方法。其诊断思想是把串联形式的混合电路，划分成模拟和数字电路两部分．并分别进行诊断。该方法计算量小、诊断定位精度高，适合于工程应用。     

Defect detection in analog and mixed circuits by neural networks using wavelet analysis

An efficient defect-oriented parametric test method for analog & mixed-signal integrated circuits based on neural network classification of a selected circuit's parameter using wavelet decomposition preprocessing is proposed in this paper. The neural network has been used for detecting catastrophic defects in two experimental analog & mixed-signal CMOS circuits by sensing the abnormalities in selected parameters, observed under defective conditions and by their consequent classification into a proper category. To reduce complexity of the neural network, wavelet decomposition is used to perform preprocessing of the analyzed parameter. Moreover, we show that wavelet analysis brings significant enhancement in the correct classification, and makes the neural network-based test method extremely efficient & versatile for detecting hard-detectable catastrophic defects in analog & mixed-signal circuits.     

Mismatch-Induced Trade-Offs and Scalability of Analog Preprocessing Visual Microprocessor Chips

This paper explores trade-offs associated with the scaling of the interaction circuits (synaptic transconductance multipliers) in visual microprocessor chips. These trade-offs are related to the necessity of maintaining analog accuracy of these circuits while taking advantage of the possibility of reducing power consumption, increasing operational speed, and reducing the area occupation, as technologies scale down into the deep submicron range.The paper does not aim to forecast the evolution of the design of general analog and mixed-signal integrated circuits in submicron technologies. It focuses on a very specific aspect of a particular type of systems. Hence, although the conclusions of the paper might appear somewhat pessimistic, deep submicron technologies define scenarios, not covered in this paper, where analog and mixed-signal circuits can take significant advantages from technology scaling. Even for the systems targeted in this paper, improvements in terms of power consumption and overall operational speed can be achieved through the use of newer architectures and circuit techniques.     

A novel simulation technique for testing analog ICs

The increasing demand for reliable and high quality mixed-signal integrated circuits necessitates a defect-oriented testing methodology. Thereby fault simulation (FS) is essential for test stimuli generation and test quality assessment. Due to the high computational effort needed, analog FS is becoming a critical factor in testing mixed-signal ICs. This paper provides a new accelerated FS approach. It is based on an improved application of the Newton–Raphson method in the analysis of similarly behaving circuits. Metrics for measuring circuits' behavior similarity are presented. The new techniques are implemented in an experimental FS tool. For sample circuits, experimental results are presented and discussed.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

Computer-aided design of analog and mixed-signal integratedcircuits

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved     

Hierarchical statistical analysis of complex analog and mixed-signal systems

With increasing process parameter variations in nanometre regime, circuits and systems encounter significant performance variations and therefore statistical analysis has become increasingly important. For complex analog and mixed-signal circuits and systems, efficient yet accurate statistical analysis has been a challenge mainly due to significant simulation and modelling time. In the past years, there have been various approaches proposed for statistical analysis of analog and mixed-signal circuits. A recent work is reported to address statistical analysis for continuous-time Delta-Sigma modulators. In this article, we generalise that method and present a hierarchical method for efficient statistical analysis of complex analog and mixed-signal circuits while maintaining reasonable accuracy. At circuit level, we use the response surface modelling method to extract quadratic models of circuit-level performance parameters in terms of process parameters. Then at system level, we use behavioural models and apply the Monte-Carlo method for statistical evaluation of system performance parameters. We illustrate and validate the method on a continuous-time Delta–Sigma modulator and an analog filter.     

Cost and performance tradeoff analysis in radio and mixed-signal system-on-package design

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC, is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally, some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.     

Making complex mixed-signal telecommunication integrated circuitstestable

This article presents a discussion of several methods that can be used to improve the testability of complex mixed-signal telecommunication integrated circuits. We begin by outlining the role of test and its impact on product cost and quality. A brief look at the pending test crises for mixed-signal circuits is also considered. Subsequently, we outline the evolution of test strategies with time, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The article also describes several circuit techniques for improving test access and providing built-in self-test solutions for telecommunication circuits     

Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits

This paper proposes a new IDD sensor for built-in self-test (BIST) applications for digital, analog, and mixed-signal circuits. This novel, wide-band, nonintrusive, process and temperature-stable IDD sensor operates up to 230 MHz, which is 2.3X faster than previously proposed designs, and occupies 78.3% less area than another competing design. A BIST utilizing this novel IDD sensor is created and tested on numerous digital circuits, as well as on an op-amp and a mixer, achieving up to 90% fault coverage, while maintaining the performance of the circuit-under-test. The experiments were implemented in 0.18-m TSMC CMOS mixed-signal technology.     

Feasibility and performance region modeling of analog and digital circuits

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.This research was supported in part by a grant from NSF (MIP-9110719)     

Cost and performance analysis for mixed-signal system implementation: system-on-chip or system-on-package?

Advances in integrated circuits and packaging technologies provided us more implementation options for mixed-signal systems. Emerging technologies are represented by system-on-chip (SoC) and system-on-package (SoP). In order to make a design decision for optimal system implementation, it is hence becoming more and more important to address the cost and performance issues for various implementation options early in a system deign phase. In this paper, we develop a modeling technique for a priori cost and performance estimations for mixed-signal system implementations. The performance model evaluates various noise isolation technologies, such as using guard rings, increasing the separation between digital and analog/RF circuitry parts, using special substrate materials (e.g., silicon-on-insulator), and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or "virtual components," yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, are considered. Finally, an efficient computation algorithm, namely COMSI, was developed for cost estimation under various mixed-signal performance constraints. Case studies for SoC and SoP integration are performed using COMSI.     

Design Approaches to Field-Programmable Analog Integrated Circuits

The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field-Programmable Mixed-Signal Arrays (FPMAs). This survey paper reviews work to date in the area of programmable analog and mixed-signal circuits. The body of work reviewed includes university and industrial research, commercial products and patents. A time-line of important achievements in the area is drawn, the status of various activities is summarized, and some directions for future research are suggested.     

Addressing noise decoupling in mixed-signal IC's: powerdistribution design and cell customization

An important and largely unexplored aspect of power distribution synthesis is cell customization. Through automatic cell customization, power I/O cell assignments and local substrate and power supply decoupling may be tailored to reduce deleterious noise effects on analog circuits in mixed-signal environments. Techniques for simultaneous power grid design (topology and sizing) and cell configuration/customization are described that allow designers to handle more difficult chip-level noise problems. Synthesis results on an industrial mixed-signal example demonstrate the effectiveness of this approach     

Compact low-power time-based conversion with noise immunity similar to digital conversion

An analog signal representation based on the inter-pulse-interval (IPI) time is presented. Voltage-to-IPI and IPI-to-voltage conversion circuits based on the representation are described. The circuits have been fabricated using a 0.35 μm mixed-signal CMOS process. Simulation and test results agree with the theory. Voltage-to-IPI conversion needs significantly less area and power than ADC and is significantly more immune to noise and other problems than using analog voltage/current signals.     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.