Self-aligned AlInAs-GaInAs heterojunction bipolar transistors andcircuits

AlInAs-GaInAs heterojunction bipolar transistors (HBTs) and static flip-flop frequency dividers have been fabricated. An f_t and an f_max of 49 and 62 GHz, respectively, have been achieved in a device with a 2×5-μm² emitter. Current-mode logic (CML) was used to implement static divide-by-two and divide-by-four circuits. The divide-by-two circuit operated at 15 GHz with 82-mW power dissipation for the single flip-flop. The divide-by-four circuit operated at 14.5 GHz with a total chip power dissipation of 444 mW     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd2Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL (FI = FO = 1) circuits and 1.3 ns at 0.15 mA for the MTL (FO = 4) circuits.     

AlGaAs/GaAs heterojunction bipolar transistors with small size fabricated by a multiple self-alignment process using one mask

A multiple self-alignment process for HBT's using one mask is developed to form emitters, emitter contacts, emitter contact leads, buried small collectors, base contacts, and base contact leads. This process makes it possible to produce HBT's of very small size and to reduce parasitic elements. An AlGaAs/GaAs HBT fabricated by the process, with an emitter 1 × 20/µm²in size and a buried collector by O⁺implantation gives a good performance of ft= 54 GHz and fmax= 42 GHz. The performance may be explained by the reduction of parasitic elements, base transit time, and collector depletion layer transit time.     

Self-aligned complementary bipolar technology for low-powerdissipation and ultra-high-speed LSIs

Fully symmetrical complementary bipolar transistors for low power-dissipation and ultra-high-speed LSIs have been integrated in the same chip using a 0.3-μm SPOTEC process. Reducing the surface concentration of the boron by oxidation at the surface of the boron diffusion layer suppressed the upward diffusion of boron from the subcollector of the pnp transistor during epitaxial growth. This enabled thin epitaxial layer growth for both npn and pnp transistors simultaneously. Cutoff frequencies of 30 and 32 GHz were obtained in npn and pnp transistors, respectively. Simulated results showed that the power dissipation is reduced to 1/5 in a complementary active pull-down circuit compared with an ECL circuit     

Self-aligned InGaP/GaAs heterojunction bipolar transistors formicrowave power application

As an alternative to AlGaAs/GaAs heterojunction bipolar transistors (HBTs) for microwave applications, InGaP/GaAs HBTs with carbon-doped base layers grown by metal organic molecular beam epitaxy (MOMBE) with excellent DC, RF, and microwave performance are demonstrated. As previously reported, with a 700-Å-thick base layer (135-Ω/sq sheet resistance), a DC current gain of 25, and cutoff frequency and maximum frequency of oscillation above 70 GHz were measured for a 2-μm×5-μm emitter area device. A device with 12 cells, each consisting of a 2-μm×15-μm emitter area device for a total emitter area of 360 μm², was power tested at 4 GHz under continuous-wave (CW) bias condition. The device delivered 0.6-W output power with 13-dB linear gain and a power-added efficiency of 50%     

JFET's fabricated in a standard IC process for bipolar transistors

A new method for the fabrication of n- and p-channel JFETs in a standard IC process for bipolar transistors is presented. Using special layout techniques, which are based on well-known principles, JFETs of good performance are obtained, provided a tightly controlled photoresist process is available.     

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BV_ceo is only defined by the one-dimensional vertical doping profile through the n⁺-emitter, the p-base, the n-intrinsic and the n⁺-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n⁺pn⁻n⁺-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BV_ceo on the transistor gain, doping level and width of the intrinsic collector.     

Vertical n-p-n bipolar transistors fabricated on buried oxide SOI

Vertical n-p-n bipolar transistors have been fabricated in silicon-on-insulator (SOI) films prepared by buried oxide implantation. Electrical device characteristics are shown to be comparable to those obtained on devices fabricated in bulk silicon, indicating no significant degradation owing to the buried oxide layer. Dielectric isolation in excess of 10¹¹Ω.cm and µ 3 × 10⁶V/cm is measured.     

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 10²⁰/cm³have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.     

Characterization of current transport in MNOS structures with complementary tunneling emitter bipolar transistors

We have extended the work of previous investigators and studied current transport in thin- (10-20 Å) and thick-(80 Å) oxide MNOS structures with complementary tunneling emitter bipolar transistors. These devices are fabricated with ion-implanted p-n and n-p junctions to distinguish the dominant carrier species in the insulator. The dominant species in thin-oxide devices is hole transport, comprising about 99 percent of the emitter current. The hole transport is suppressed in the thick-oxide structures, where the dominant carriers are electrons. Electron impact ionization multiplication is observed in thick-oxide structures.     

GaAs/AlGaAs heterojunction emitter-down bipolar transistors fabricated on GaAs-on-Si substrate

GaAs/AlGaAs heterojunction bipolar transistors with emitter-down structure were fabricated on GaAs-on-Si substrate for the first time. A maximum current gain of 25 was measured at a collector current density of 6250 A/cm². This value is comparable with that from similar devices fabricated on GaAs substrates. This result, along with previous work on large-scale integration of emitter-down transistors, demonstrates the potential for high-level integration of bipolar devices on GaAs-on-Si substrates.     

Self-aligned gate and source drain contacts in inverted-staggereda-Si:H thin-film transistors fabricated using selective area siliconPECVD

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm² /Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10^-11 A with -10 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10     

Self-aligned bottom-gate submicrometer-channel-length a-Si-:Hthin-film transistors

Fully self-aligned bottom-gate thin-film transistors (TFTs) fabricated by using a back substrate exposure technique combined with a metal lift-off process are discussed. Ohmic contact to the sources and drains is accomplished by a 40-nm-thick layer of phosphorous-doped microcrystalline silicon. Devices with channel lengths ranging from 0.4 to 12 μm are processed with overlap dimensions between the gate and the source and the gate and the drain ranging from 0.0 to 1.0 μm. Analysis of the conductance data in the linear voltage regime reveals a parasitic drain-to-channel and source-to-channel resistance that is 14% of the channel resistance for a 10-μm device and 140% for a 1-μm device. Thus, increase in the device speed caused by reducing the channel length does not follow expected behavior. A similar situation exists in the nonlinear regime. The on-current of the devices starts to saturate below channel lengths of 2 μm. Current on/off ratios taken at V_d=5 V and V_G=15 V and 0 V, respectively, are approximately 1×10⁶ for the 1- and 12-μm-long devices. The on/off ratio is reduced to 1×10⁵ for the 0.4-μm device     

Self-aligned Ti germanosilicide formation on a polycrystalline Si/SiGe/Si extrinsic base for SiGe heterojunction bipolar transistors

This work reports our investigation of a microstructure of self-aligned Ti germanosilicide made on polycrystalline Si/SiGe/Si multilayers. The existence of the SiGe layer restricted the growth of the Ti germanosilicide layer and produced protrusions penetrating the underlying polycrystalline layer. Each protrusion corresponded to a stacking-faulted single grain of the C49 phase. The microstructure of the thin Ti germanosilicide layer and the deep protrusions caused an increase of the sheet resistance and the contact resistivity of the extrinsic base region. The raised contact resistivity led to a degradation of radio frequency (RF) and noise characteristics of the SiGe heterojunction bipolar transistor (HBT).     

Improved cutoff frequency in vertical bipolar transistors fabricated with focused ion beam lateral base profiles

Improved high-frequency performance in vertical bipolar transistors in which the active base region is fabricated with focused ion beam (FIB) lateral doping profiles is demonstrated. Profiles which reduce base resistance, current crowding, and high-level injection effects have the most significant effect on high-frequency characteristics.     

Self-aligned flexible organic thin-film transistors with gates patterned by nano-imprint lithography

Many applications that rely on organic electronic circuits still suffer from the limited switching speed of their basic elements – the organic thin film transistor (OTFT). For a given set of materials the OTFT speed scales inversely with the square of the channel length, the parasitic gate overlap capacitance, and the contact resistance. For maximising speed we pattern transistor channels with lengths from 10 μm down to the sub-micrometre regime by industrially scalable UV-nanoimprint lithography. The reduction of the overlap capacitance is achieved by minimising the source–drain to gate overlap lengths to values as low as 0.2 μm by self-aligned electrode definition using substrate reverse side exposure. Pentacene based organic thin film transistors with an exceptionally low line edge roughness <20 nm of the channels, a mobility of 0.1 cm²/Vs, and an on–off ratio of 10⁴, are fabricated on 4″ × 4″ flexible substrates in a carrier-free process scheme. The stability and spatial distribution of the transistor channel lengths are assessed in detail with standard deviations of L ranging from 185 to 28 nm. Such high-performing self-aligned organic thin film transistors enabled a ring-oscillator circuit with an average stage delay below 4 μs at an operation voltage of 7.5 V.     

High-performance low-base-collector capacitance AlGaAs/GaAsheterojunction bipolar transistors fabricated by deep ion implantation

Low-base-collector capacitance (C_bc) AlGaAs/GaAs HBTs with f_MAX>200 GHz and f_T=52 GHz have been fabricated. With co-implants of high energy, high dose He⁺ and H⁺ ions through the external base layer, part of the heavily doped n⁺ sub-collector was compensated leading to a decrease in the extrinsic portion of C_bc. The implants caused only a slight increase of base resistance. Using this approach in combination with a standard low dose, shallow collector compensating implant, C_bc of double implanted HBT's can be reduced by more than 35%     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

Herb's bipolar transistors

The profound influence of Herbert Kroemer's ideas on the development of high-performance bipolar transistors is described. The historical context and subsequent development of innovations such as the drift base, achieved through concentration gradients and later with semiconductor bandgap grading, the use of wide bandgap emitters, concepts of collector-up transistors, and the introduction of new heterojunction materials, are reviewed