Lateral complementary transistor structure for the simultaneous fabrication of functional blocks

Heretofore, the schemes for fabricating a complementary transistor structure in a monolithic functional block entailed either some additional, difficult-to-control processing steps or a sacrifice in isolation of the collector regions of one type of transistor. This paper describes an isolated p-n-p transistor structure fabricated by the same technique used for the conventional all n-p-n transistor functional block without any additional processing steps. The basic p-n-p transistor has a lateral structure. During the p-type base diffusion of the n-p-n transistor, two concentric p-type regions at close distance are selectively diffused into an isolated n- type region such as that used for the collector of an n-p-n transistor. The center p-type diffused region forms the emitter and the outer ring forms the collector. The n-type spacing between these two regions serves as the base. The current gain of this transistor is not high, typically around unity. However, by amplifying the collector current of the p-n-p transistor with an n-p-n transistor, the composite transistor acts like a high gain p-n-p transistor and the composite current gain can be made comparable to that of the n-p-n transistor in the same functional block. The lateral complementary transistor has been used extensively and successfully for the fabrication of linear functional blocks such as those used in the Advanced Minuteman Program.     

Measurement of collector and emitter resistances in bipolartransistors

New DC methods to measure the collector resistance R_C and emitter resistance R_E are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R_C. R_E is obtained from the measured lateral portion of R_C and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R_C on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R_C is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R_E a value for the specific contact resistance for the polysilicon emitter contact of ρ_c≅50 Ω-μm² is obtained     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. Tlris leads to the formation of p/sup +/ -n/sup +/ junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p/sup +/-n/sup +/ junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

A vertically isolated self-aligned transistor—VIST

A vertically isolated self-aligned transistor (VIST) has been developed to make possible high-speed low-power dissipation bipolar devices suitable for LSI. This VIST consists of a bird's beak free oxide isolated structure and a high impurity density inactive base self-aligned to the polysilicon emitter. A flat emitter transistor with a self-aligned base is developed by forming an inactive high impurity density base region with an ion-implantation method using a polysilicon emitter as a mask. The transistors exhibit uniform current gain even to current levels as low as 10^-8A. The ftvalue of this transistor is 6 GHz. The ring oscillators and counter are fabricated using the 13 × 6 µm²transistor cell. The power and delay product is 0.12 pJ.     

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.     

Self-aligned bipolar transistors for high-performance and low-power-delay VLSI

An n-p-n bipolar transistor structure with the emitter region self-aligned to the polysilicon base contact is described. The self-alignment results in an emitter-to-base contact separation less than 0.4 µm and a collector-to-emitter area ratio about 3:1 for a two-sided base contact. This ratio can be less than 2:1 for a base contacted only on one side. The vertical doping profile can be optimized independently for high-performance and/or high-density and low-power-delay circuit applications. The technology, using recessed oxide isolation, was evaluated using 13-stage nonthreshold logic (NTL) and 11-stage merged-transition logic (MTL) ring-oscillator circuits designed with 2.5 µm design rules. For transistors with 200-nm emitter junction depth the common-emitter current gain for polysilicon emitter contact is typically 2-4 times that for Pd2Si emitter contact. There is no observable circuit performance degradation attributable to the polysilicon emitter contact. Typical observed per-stage delays were 190 ps at 1.3 mW and 120 ps at 2.3 mW for the NTL (FI = FO = 1) circuits and 1.3 ns at 0.15 mA for the MTL (FO = 4) circuits.     

Improved bipolar transistor performance in a VLSI CMOS process

Bipolar n-p-n transistors have been successfully fabricated on a high-performance n-well VLSI CMOS process incorporating an additional mask and implant step. A double active-base implant was utilized to control the base surface concentration and the transistor characteristics separately. High forward common-emitter current gain and collector-emitter breakdown voltage can be achieved by this process. n-p-n transistors with βf= 100, BVCE0= 9.0 V, and BVCB0= 23 V can be easily fabricated on this scaled VLSI CMOS process.     

Investigation of boron diffusion in polysilicon and its applicationto the design of p-n-p polysilicon emitter bipolar transistors withshallow emitter junctions

Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow (<500 Å) p-n-p polysilicon emitter bipolar transistors. It is shown that diffusion and electrical activity problems are encountered with boron polysilicon emitters which are not present with arsenic. Base current and emitter resistance are measured on shallow p-n-p polysilicon emitter transistors, and it is shown that the use of a deliberately grown interfacial oxide layer can decrease the base current by a factor of 10 and increase the emitter resistance by a factor of around 2. Comparisons with identical n-p-n polysilicon emitter transistors show that the modeled interfacial oxide, tunneling parameters for n-p-n and p-n-p devices are inconsistent     

A new complementary monolithic transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process a pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure.     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

A simplified fully implanted bipolar VLSI technology

An implanted n-p-n bipolar transistor structure named Isoplanar Z II (currently, being marketed as FAST-Z technology) with reduced process and masking steps is described. The simplification is achieved by employing self-aligned-transistor (SAT) masking, ion-implantation techniques to provide impurity doping, and using one common annealing cycle for collector, base, and emitter implantations. The device structure reduces design constraints through use of self-aligned field implantation and SAT mask for contact window definition. Submicrometer emitter widths are obtained by step and repeat optical photolithographic tool and two-dimensional effect on current gain due to sidewall injection is also studied. This technology is used to demonstrate 13-15 ns TAA, 4K static RAM and minimum delay of 250 ps per gate, gate array products.     

High speed integrated injection logic (I/SUP 2/L)

High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a very thin epitaxial layer and ion implantation. Electronic improvements which decrease the charge storage in both the p-n-p and n-p-n transistor are discussed. Analytic expressions are derived which show the consequences for the minority charge stored in the base of the n-p-n transistor and for the influences on the current noise margin. A tradeoff between noise margin and speed is then made. Besides the reduction in delay time, another attractive aspect of this approach is that it allows a simple layout design. By using separate p-n-p and n-p-n transistors, the position of the n-p-n transistors can be adapted to the logic wiring because there is no limitation in the number of crossovers. Some experimental results are given. A minimum value of the propagation delay time of 3 ns has been measured.     

The use of an interface anneal to control the base current andemitter resistance of p-n-p polysilicon emitter bipolar transistors

The effects of an interface anneal on the electrical characteristics of p-n-p polysilicon-emitter bipolar transistors are reported. For devices with a deliberately grown interfacial oxide layer, an interface anneal at 1100°C leads to a factor of 15 increase in base current, and a factor of 2.5 decrease in emitter resistance, compared with an unannealed control device. These results are compared with identical interface anneals performed on n-p-n devices, and it is shown that the increase in base current for p-n-p devices is considerably smaller than that for the n-p-n devices. This result is explained by the presence of fluorine in the p-n-p devices, which accelerates the breakup of the interfacial layer     

Complementary MOS—Bipolar transistor structure

Bipolar transistors can be used to increase the driving capabilities of complementary MOS transistors while retaining the low power dissipation feature. The fabrication of n-p-n bipolar transistors is compatible with the fabrication of the complementary MOS transistors in a monolithic structure. Common collector n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter, a diffused p^-isolation region as base and an n^-substrate as collector with a hfegreater than 100. Lateral n-p-n transistors can be fabricated using a diffused n⁺source-drain region as emitter and collector, and p^-isolation region as base with a hfegreater than 10.     

Monolithic integration of complementary HBTs by selective MOVPE

The monolithic integration of n-p-n and p-n-p heterojunction bipolar transistors (HBTs) through the use of selective metal organic vapor phase epitaxial regrowth is discussed. This was accomplished by masking, patterning, and etching a p-n-p HBT wafer and then selectively regrowing an n-p-n structure in the etched areas. The selective epitaxial regrowth did not degrade the current gain of the p-n-p structure. Several complementary amplifier circuits were fabricated and tested successfully, demonstrating the feasibility of a monolithic complementary HBT technology     

I/SUP 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.     

A quasi-one-dimensional analysis of small-signal current gains in lateral transistors

A small-signal analysis of lateral p-n-p transistors has been made using a quasi-one-dimensional model. This model consists of a lateral p-n-p intrinsic transistor section and a vertical p-n-n⁺-p parasitic transistor section. The effect of the retarding electric field of the n⁺subdiffused layer is incorporated explicitly into the model. Besides, the field-dependent nonunity emitter efficiency of lateral transistors has also been taken into account. From the solutions of continuity equations in the base regions, closed-form expressions for small-signal current gains are obtained in terms of an ac field factor which is defined by the geometry and doping profile of the device. Frequency dependence of current gains evaluated from this analysis compares favorably with the results from an earlier two-dimensional analysis. The simplicity of the model and its reasonably good accuracy are expected to be helpful in the modeling of lateral transistors used in linear integrated circuits.     

High-speed, high-current-gain p-n-p InP/InGaAs heterojunctionbipolar transistors

p-n-p InP/InGaAs heterojunction bipolar transistors (HBTs) are reported for the first time. The transistors, grown by metal organic molecular beam epitaxy (MOMBE), exhibited maximum DC current gain values up to 420 for a base doping level of 4×10¹⁸ cm^-3 . Small-signal measurements on self-aligned transistors with 3-μm×8-μm emitter area indicated the unity gain cutoff frequency value of 10.5 GHz and the inferred maximum frequency of oscillation of 25 GHz. The results clearly demonstrate the feasibility of complementary integrated circuits in the InP material system