Submicrometer device design for hot-electron reliability and performance

Hot-electron stressing effect on different lightly doped drain device (LDD), As/P, and conventional As source/drain device structures are investigated. Increasing the overlap between the gate and drain is found to reduce hot-electron degradation significantly when stressed under the same substrate current level. By increasing the gate-to-drain overlap, it is possible to design LDD and As/P devices with a shorter n-region and still have good hot-electron reliability. These devices have better current drive and are scalable down to the submicrometer region. The As/P device with a short n-region is a good candidate for a submicrometer VLSI device because of the simplicity in processing, the good device performance, and the low susceptibility to hot-electron degradation.     

Simple gate-to-drain overlapped MOSFETs using poly spacers for highimmunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer     

Design for suppression of gate-induced drain leakage in LDD MOSFETsusing a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10¹⁴/cm², the LDD and fully overlapped LDD devices exhibit similar GIDL current     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Characterization and modeling of edge direct tunneling (EDT)leakage in ultrathin gate oxide MOSFETs

This paper examines the edge direct tunneling (EDT) of electron from n⁺ polysilicon to underlying n-type drain extension in off-state n-channel MOSFETs having ultrathin gate oxide thicknesses (1.4-2.4 nm). It is found that for thinner oxide thicknesses, electron EDT is more pronounced over the conventional gate-induced-drain-leakage (GIDL), bulk band-to-band tunneling (BTBT) and gate-to-substrate tunneling, and as a result, the induced gate and drain leakage is better measured per unit gate width. A physical model is for the first time derived for the oxide field E_OX at the gate edge by accounting for electron subband in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of drain extension. Once fox is known, an existing DT model readily reproduces EDT I-V consistently and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to EDT is projected as well     

Performance and reliability evaluation of high dielectric LDDspacer on deep sub-micrometer LDD MOSFET

High dielectric LDD spacer has been proposed to achieve both reliability and performance improvement on the scaled LDD MOSFET's. However, the sidewall polyoxide and spacer bottom oxide required for process reliability issue will adversely limit the DC performance improvement gained by using high dielectric LDD spacer. AC performance is evaluated by the transconductance cutoff frequency determined by the transconductance, G_M and total gate capacitance, C_GG . For deep-submicron MOSFET's, the dominance of gate to source/drain overlap capacitance in C_GG has significant impact on the AC performance. The increase of C_GG due to the enhanced fringe field from high dielectric LDD spacer significantly dominates over the increase of transconductance, and then deteriorates the AC performance. As the reliability issue is concerned, the key doping profile, N^- source/drain lateral diffusion profile was obtained from the two dimensional process simulator SUPREM-IV corresponding to wide range of LDD N^- doses. The optimized N ^- dose designed for hot carrier reliability issue (under V _GS-V_T=0.5 V_DS operation) is located around 2×10¹³ cm^-2 for both conventional LDD (denoted as OLDD in this paper) and high dielectric LDD (HLDD) devices. However, the improvement achieved by using HLDD instead of OLDD devices is then turned out to be insignificant under this optimized N^- dose condition     

A theoretical study of gate/Drain offset in LDD MOSFET's

A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor, indicating the effectiveness of an LDD design in reducing the peak channel field, is used to compared LDD structures with, without, and with partial gate/drain overlap. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor (FRF) and the series resistance are presented for the three cases. Structures with gate/drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate/drain offset can cause the rise of channel field and substrate current at large gate voltages. Good agreement with simulations is obtained.     

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

In this paper,RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency (ft),maximum oscillation frequency (fmax),intrinsic gain and admittance (Y) parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current (ION) of about 0.2 mA and less leakage current (IOFF) of 29 fA is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance (gm),higherf and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher fmax of 985 GHz is obtained for drain doping of 5 × 1017 cm-3 because of the reduced gate-drain capacitance (Cgd) with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.     

Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

Annealing of oxide fixed charges (QF) under polysilicon gate in scaled MOS structures was studied. Our results indicate that, even for a gate width as small as 1.25 µm, QFunderneath the polysilicon gate is unaffected by further processing steps, including high-temperature oxidizing ambients. In other words, the QFtriangle reduces to a horizontal line, even for scaled down polysilicon gate MOS devices. This result has important practical implications, because poly-Si gate is the dominating MOS technology today. A two-dimensional oxygen diffusion model is proposed to explain this phenomenon. Numerical solution was carried out based on the finite difference method. It will be shown that the polysilicon gate not only acts as a barrier to oxygen above the gate oxide, it also keeps oxygen away from the SiO_{2}- Si-substrate interface under the gate edges, thus very effectively shielding the gate oxide from the ambient.     

Gate-induced drain-leakage in buried-channel PMOS-a limiting factorin development of low-cost, high-performance 3.3-V, 0.25-μmtechnology

This paper presents a low cost 0.25-μm technology with low standby power for 3.3 V applications. It is shown that as a single gate oxide n-type polysilicon gate technology is scaled, gate-induced drain-leakage (GIDL) in buried-channel PMOS becomes a serious limiting factor in achieving low standby power. The impact of technology choices such as spacer material, spacer width and poly reoxidation conditions on PMOS GIDL is discussed. A technology that successfully limits PMOS leakage is presented     

GaN基HEMT器件结构设计及其性能仿真北大核心

利用Silvaco TCAD器件模拟软件研究了AlGaN/GaN高电子迁移率晶体管(HEMT)器件势垒层的厚度、沟道宽长比和掺杂浓度对器件的转移特性和跨导曲线的影响。结果表明,器件势垒层厚度的变化可以调节器件的电流开关比和开启电压,实现由耗尽型器件向增强型器件的转变;沟道宽长比的改变可以调节器件的开启电压,并且随着沟道宽长比的增加,栅极电压控制量子阱中二维电子气的能力增强;势垒层适量掺杂提高了输出电流,并且使跨导的峰值增大,但过度掺杂会造成器件不易关断情况出现。     

Edge hole direct tunneling leakage in ultrathin gate oxidep-channel MOSFETs

This paper examines the edge direct tunneling (EDT) of holes from p⁺ polysilicon to underlying p-type drain extensions in off-state p-channel MOSFETs having ultrathin gate oxides that are 1.2 nm-2.2 nm thick. It is for the first time found that for thinner oxides, hole EDT is more pronounced than both conventional gate-induced drain leakage (GIDL) and gate-to-channel tunneling. As a result, the induced gate and drain leakage is more accurately measured per unit gate width. Terminal currents versus input voltage are measured from a CMOS inverter with gate oxide thickness T_OX=1.23 nm, exhibiting the impact of EDT in two standby modes. For the first time, a physical model is derived for the oxide field E_OX at the gate edge by accounting for the heavy and light holes' subbands in the quantized accumulation polysilicon surface. This model relates E_OX to the gate-to-drain voltage, oxide thickness, and doping concentration of the drain extension. Once E_OX is known, an existing direct tunneling (DT) model consistently reproduces EDT current-voltage (I-V), and the tunneling path size extracted falls adequately within the gate-to-drain overlap region. The ultimate oxide thickness limit due to hole EDT is projected     

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.     

Self-aligned maskless chan stops for IGFET integrated circuits

Many IGFET integrated circuits incorporate a region of enhanced doping under the field oxide to eliminate the possibility of spurious inversion layers causing leakage between devices. Using chemical predeposition technology, this typically requires a photolithographic step to define the region of enhanced doping. This paper describes a structure in which a nonselective implantation that forms an enhanced doping over the entire wafer is selectively compensated through windows patterned in the field oxide to form gate oxide regions. Threshold voltage control is excellent and identical to control devices fabricated without chan stops. The channel hole mobility is normal and no undesirable effects have been observed if care is exercised in controlling the implanted doses. MOS characteristics are normal and are not affected by residual ion damage. Typical parameters for p-channel devices are shown for various levels of compensation, resulting in gate threshold voltages ranging from -0.5 →-2.2 V for p-channel devices. The field threshold is -18.V for a 7000 Å thick field oxide and hole mobilities range from 190 to 290 cm²/V.s.     

Submicrometer salicide CMOS devices with self-aligned shallow/deepjunctions

The use of triple-layer oxide/nitride/PETEOS (plasma-enhanced TEOS) gate spacer, CMOS (T-MOS) structure to form shallow/deep junctions with the deep junction self-aligned to the silicide layer on the source/drain area of submicrometer CMOS devices is discussed. Due to the disposable PETEOS spacer layer, only two masks (one for each channel) are needed to form this source/drain junction signature. A T-MOS structure of 0.5-μm physical gate length has been demonstrated with good device characteristics and ideal junction leakage properties. This T-MOS process, with its moderated doped drain (MDD) structure, is a promising device choice for deep-submicrometer CMOS devices     

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.     

Short channel MOSFET model using a universal channel depletionwidth parameter

We verified a critical rendition that short channel effects depend on junction depth, and showed that junction depth by itself is not important for improving short channel immunity. The depletion region width of a short channel device changes significantly depending on the location along the channel. We proposed a universal channel depletion width parameter that effectively expresses this dependence. Using this parameter, we solved a two-dimensional (2-D) potential distribution and derived a threshold voltage model. The model reproduces the numerical data of sub-0.1-μm gate length devices, including channel doping concentration, gate oxide thickness, drain voltage, and back bias dependencies     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

应变Si1-xGex沟道PMOSFET空穴局域化研究

为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。     

三栅MOSFET阈值电压模型

根据三栅(TG)MOSFET二维数值模拟的结果,分析了TG MOSFET中的电势分布,得出了在硅体与掩埋层接触面的中心线上的电势随栅压变化的关系;通过数学推导,给出了基于物理模型的阈值电压的解析表达式;并由此讨论了多晶硅栅掺杂浓度、硅体中掺杂浓度、硅体的宽度和高度以及栅氧化层厚度对阈值电压的影响;得出在TG MOSFET器件的阈值电压设计时,应主要考虑多晶硅栅掺杂浓度、硅体中掺杂浓度和硅体的宽度等参数的结论。