自激振荡虚拟实验电路设计及其仿真

本文给出了演示自激振荡现象的负反馈放大电路,该电路仅由运放和RC元件构成,既便于进行理论推导、分析,也便于进行仿真演示,非常适合于教学之用.根据自激振荡的起振条件,给出了反馈网络电阻参数应满足的关系.利用电路仿真软件Multisim对电路的特性进行了分析.仿真结果验证了理论分析结果.本文的讨论可供讲授电路理论或模拟电子技术课程的教师参考.     

DAC,ADC电路的仿真实验研究

利用EDA技术进行复杂实验的研究与开发,是改革传统数字电路实验教学模式的有效途径,能帮助学生熟悉和掌握先进的电路实验方法和技能。通过实例分析和实验结果对比,能较快掌握在实践中广泛应用但在做硬件实验中效果不佳的DAC,ADC电路的原理、性能、应用和测试方法。     

Computer-Aided Synthesis of Planar Circuits

This paper presents a fully computer-oriented iterative synthesis of an open-boundary planar circuit having an impedance matrix with prescribed poles and residues. A starting circuit pattern is given first, and it is represented by a finite number of parameters. Those parameters (and hence, the pattern) are then iteratively modified by using the Newton-Raphson method to realize the prescribed circuit characteristics. When the numbers of given poles and coupling ports are relatively small, the results are satisfactory both in the computing time and accuracy. Some numerical examples are given.     

基于Multisim的三相电路仿真分析

在生产与生活中三相电路的应用最为广泛，针对三相电路运行工况的实验就显得重要而且必然，然而实际的三相电路实验不仅危险性较大，而且一些故障性试验较难进行。电路仿真软件Multisim提供了适用于三相电路仿真的各种元件模型及分析工具，利用该软件对三相电路的3种不对称短路故障进行了仿真分析，与理论分析比较的结果表明仿真软件效果理想。通过虚拟实验分析了负载变化对三相电路的影响，从而得出了照明线路为保持各相电压不变一般采用三相四线制的结论。两组实验表明利用Muttisim可以方便快捷地对三相电路进行各种实验分析。优点明显．适合在电工实验中推广。     

Synthesis and Optimization of Combinational Interface Circuits

We describe an algorithm for interface synthesis and optimization for embedded system components such as microprocessors, memory ASIC, and network subsystems. The algorithm accepts the timing characteristics of two chips as input, and generates a combinational interface circuitry to implement communication between them. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections employing a 0-1 ILP formulation to minimize wiring area and dynamic power consumption in the resulting interface circuit. In the second part, we use a novel encoding method to synthesize connections between chips which require additional gates in the interface circuit. Experiments show that our algorithm is very effective in practice.     

集成电路的可靠性模型与模拟

随着集成电路（ＩＣ）尺寸的缩小，集成度的提高，必须在设计阶段对其可靠性进行预测。文中在阐述了与ＩＣ可靠性密切相关的热载流子效应、时间决定的介质击穿效应、互连线电迁移效应、双极晶体管退化效应及其模型后，给出了ＩＣ可靠性模拟的一般概念、方法和部分模拟结果。     

纳米器件特性的计算机模拟

随着微细加工技术与纳米科技的发展 ,纳米器件必将成为下一代集成电路的基础。纳米器件模型的建立与计算机模拟对于实验有着重大的指导意义。文中综述了纳米器件的几种输运模型及其模拟结果 ,并对纳米器件物理模型及其辅助设计提出了设想。     

GaAs数字单片电路的计算机模拟

本文在开发并确立通用电路分析程序SPICE3A7的GaAs MESFET模型及相应模型参数提取方法的基础上,对GaAs MESFET器件及相关BFL.单元电路进行了直流和瞬态的计算机模拟和部分优化,取得了较好结果;并对研制中的分频器电路设计进行了计算机研究.     

模拟电路功能级仿真

多级仿真是当前电路ＣＡＤ主要研究方向之一。本文首先提出模拟电路的两种行为模型，接着提出电路频域行为模型自动建立方法，同时给出两种模型功能级仿真的实现算法，文章最后给出功能级仿真实例。     

用Multisim 8软件实现电子电路的仿真

介绍了Multisim 8软件仿真功能的特点,并通过实例说明了用Multisim 8软件进行仿真分析的具体方法,简单介绍了设置参数和进行仿真操作的方法.     

Protel DXP环境下电路仿真分析方法

介绍了Protel DXP的新功能及其仿真分析的特点，举例说明了利用Protel DXP进行电路仿真分析的方法．     

OrCAD PSpice在电子线路实验仿真研究

针对目前高校学生人数多、仪器不足的矛盾和仿真实验的现状,作为分析与仿真能力板佳的专业软件,OrCADPspice的应用范围越来越广。文章简要介绍了高校在电子和电气等专业开设PSpice课程的必要性,然后从应用PSpice对电路仿真的放大器电路静态工作点求解及交流扫描分析的幅频特性两个实例,理论和仿真相吻合,论证了该软件在电子线路课程教学方面的可行性,提高了学生的兴趣,可以有效解决传统实验的缺陷。     

脉冲变压器MOSFET栅极驱动电路分析与仿真

为了使BUCK变换器中MOSFET能够浮地工作,采用脉冲变压器构成其栅极驱动电路.分析驱动电路的结构和工作原理,对脉冲变压器进行设计,并给出增大磁化电感和减小漏感的方法,从而有效传输驱动波形,有利于降低MOSFET的损耗,提高BUCK变换器的效率.通过软件和实验对脉冲变压器驱动电路进行电路仿真和实验验证.     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

基于Verilog-A的模拟电路行为模型及仿真

分析了模拟硬件描述语言Verilog—A的特点及模型结构,根据仿真速度和仿真精度的折衷考虑,设计实现了模拟开关、带隙基准电压源及运放的Verilog—A行为模型。根据数模转换器(13AC)的特性,基于Verilog—A设计了DAC参数测试模型,也建立8位DAC的行为模型。所有行为模型都在Cadence Spectre仿真器中实现了仿真验证。     

基于Protel DXP的电路设计与仿真

Protel DXP是最流行的电路设计自动化软件之一,是Protel的最新版本。Protel DXP可以对电路进行设计仿真,它提供的仿真器比较简单,基本能满足电路设计的要求,利用它可以节省时间,缩短开发周期,还可以节省成本。文中在介绍Protel DXP的新型功能特点后,针对典型的滤波电路进行了设计,并利用仿真器进行了仿真,给出了仿真结果和分析。     

电磁兼容仿真中的算法研究

文章介绍了通信系统中典型的电磁兼容问题——电磁干扰,以及几种常用的电磁兼容仿真算法,并对各种算法进行洋细分析,提出了适用于通信系统的电磁兼容仿真算法,以供相关工程设计人员作为参考。     

Hybrid Fault Simulation for Synchronous Sequential Circuits

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.     

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

In this paper we propose a method for synthesizing sequentialcircuits to reduce the number of gates and flip-flops by removingboth combinationally and sequentially redundant faults. In order toremove sequentially redundant faults these faults are converted intocombinationally redundant faults by using retiming techniques and thecombinationally redundant faults can be removed by using a testpattern generation method for combinational circuits. To simplify agiven circuit retiming is utilized for two purposes in thismethod. One is to find sequentially redundant faults and another is toreduce the number of flip-flops and gates. Before and after eachretiming the combinationally redundant faults are removed.Experimental results for ISCAS 89 benchmark circuits show that thismethod can remove many of sequentially redundant faults and canreduce a large number of gates and flip-flops.