Am improved tail current source for low voltage applications

A new current source for low-voltage applications is proposed. This current source is well suited for biasing differential pairs and source followers. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured to be 8 MΩ. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully balanced and single-ended differential amplifiers     

一种新型的0．5V全差分运放的设计

提出一种新型的工作在0．5V电源电压下两级低压全差分运放,该运放结构是带有共模反馈的密勒补偿运放,拥有更强的抗噪声能力和共模电源电压抑制能力,带宽更大,提高了系统的稳定性。输入信号由晶体管的栅极加入,这点与传统的电路结构相吻合,并采用衬底自偏置解决了阈值电压对电源电压降低的限制,更易于实现。该运放结构是基于SMIC0．18μm标准CMOS工艺,HSpice仿真结果表明,这种结构的开环增益可以达到76dB,单位增益带宽150MHz。     

A Realization of a Low-Voltage Differential-Output OTA Using a Simple CM Amplifier

A technique for realization of low-voltage OTAs is presented in this letter. A very low-voltage differential-output OTA is realized by employing a new common-mode amplifier in the common-mode feedback circuit. The results of PSpice simulations are shown. The proposed OTA can operate at a 0.9 V supply voltage.     

Low-voltage CMOS programmable gain amplifier for UHF applications

A CMOS programmable gain amplifier suitable for low-voltage operation over the very high frequency range is presented. The scheme is based on a very simple common-mode feedforward pseudo-differential pair with resistive loads. Post-layout results for a 1.8 V-0.18 mum CMOS design show a linear-in-dB programmable gain from 0 to 12 dB with a -3 dB bandwidth above 1.4 GHz and power consumption below 17 mW over all the gain range.     

A new active common-mode EMI filter for PWM inverter

This paper presents a new active common-mode electromagnetic interference (EMI) filter for the pulse-width modulation (PWM) inverter application. The proposed filter is based on the current sensing and compensation circuit and it utilizes a fast transistor amplifier for the current compensation. The amplifier utilizes an isolated low-voltage DC power supply for its biasing and it is possible to construct the active filter independent of the source voltage of the equipment. Thus the proposed active filter can be used in any application regardless of its working voltage. The effectiveness of the proposed circuit has been verified by experimental results.     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.     

Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell

A CMOS differential amplifier cell for minimum supply requirements is presented. The solution uses transistors in strong inversion and an original biasing scheme that exploits the bulk terminals of the transistor pair to accurately set the quiescent current and provide common-mode control. As a result, we avoid the use of the tail current source adopted in traditional differential stages. An implementation based on an auxiliary switched-capacitor network used in the feedback control loop is proposed and theoretically examined. Measurements on a prototype fabricated in a standard 0.35- mum technology (with threshold voltages around 0.5 V) and powered with 1.2 V show an error in the bias current of about 15% with respect to the expected value. It was found that the obtained overall performance is comparable to that of a traditional long-tailed differential pair that uses a higher supply of 1.5 V.     

High CMRR CMOS current operational amplifier

A CMOS realisation of a current operational amplifier operating under 3 V supply voltage is presented. The proposed implementation provides very high common-mode rejection. Results of HSPICE simulation show a high open loop current gain of 67 dB, a gain-bandwidth product of -100 MHz and a common-mode rejection ratio of 150 dB     

Low-voltage constant-gm rail-to-rail CMOS operational amplifier input stage

This paper presents a rail-to-rail constant-g_m operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-g_m by using dummy input differential pairs. The problem which causes total g_m variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower g_m variation. The g_m of this Op Amp’s input stage varies around ±2%.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results

In this paper, we describe a novel low-voltage class-AB operational amplifier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18-mum CMOS process technology. Measurements under 5 pF and 10 kOmega load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 muW with an input referred noise of 160 nV/radicHz at 1 kHz. Opamp-B consumes only 40 muW and exhibits a lower input referred noise of 107 nV/radicHz at 1 kHz     

Comparison of Quasi-/Pseudo-Floating Gate Techniques and Low-Voltage Applications

The quasi- or pseudo-floating gate (QFG) technique addresses a key issue with the floating-gate MOS transistor technique, by using ultra-high resistances to provide dc paths to otherwise floating nodes. Several ways have been suggested to implement the quasi-infinite resistors (QIRs). In this paper, basic QIR structures are analyzed and compared, and three sources of error, dc offset, signal distortion, and signal-dependent offset, are defined. Then, through simulations and experiments, the suitability of several QIR implementations for use in various applications is compared. A particular QIR implementation is found to minimize dc offset, but requires voltage swings to be limited to less than a diode turn-on voltage. Some application circuits using quasi-floating gate are presented, including a QFG translinear geometric-mean circuit and QFG low-voltage fully-differential amplifiers with QFG common-mode feedback using several QIR structures. Measurements on current-mode QFG circuits exhibit large offsets and very long turn-on transients, which could limit practical application of this technique. Inchang Seo received B.S. and M.S. degrees in physics from Hanyang University, Seoul, Korea, in 1988 and 1990. He also received M.S. and Ph.D degrees in electrical and computer engineering from the University of Florida, Gainesville, Florida, in 2000 and 2004, respectively. During 1990–1997, he worked as a researcher at the Agency for Defence Development (ADD), Chinhae, Korea. His responsibility was design, development, and evaluation of underwater acoustic transducers and sonar systems which were based on piezoelectric, magnetostrictive, and fiber-optic transducers. His main research interests involve low-voltage, low-power, high-precision analog and mixed-signal integrated circuit design including low-voltage wide-band DS data converters, precise bias circuit blocks, low-power charge transfer amplifiers and filters, floating-gate CMOS analog circuits, and quasi-floating gate analog applications. Robert M. Fox received the B. S. degree in Physics from the University of Notre Dame in 1972, and M. S. and Ph. D. degrees in Electrical Engineering from Auburn University in 1981 and 1986, respectively. Since 1986 he has been on the Electrical and Computer Engineering faculty at the University of Florida, where he is an Associate Professor. Dr. Fox's research emphasizes circuit design and modeling for advanced IC technologies. He has worked on a variety of topics, including analog circuit design, cryogenic electronics, circuit design with SOI, radiation response of semiconductors, noise modeling, and modeling of transistor self-heating. Currently his research interests center on design-oriented analysis of analog integrated circuits, including low-voltage circuit techniques, design of log-domain circuits, analog test strategies and transistor modeling. Dr. Fox is a member of the Analog Signal Processing Technical Committee of the Circuits and System Society, having served as Committee Chairman and ISCAS Track Chair. He is a member of the Analog/Mixed-Signal Technical Committee for the IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM).     

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamicrange

The design of a low-voltage and low-power ΔΣ analog-to-digital (A/D) converter is presented. A third-order single-loop ΔΣ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV ΔΣ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-μW power consumption     

基于电阻电流镜的低压灵敏放大器设计

提出一种适用于低压快闪存储器的电流模式的低压灵敏放大器.该灵敏放大器在基准电流产生电路中使用电阻电流镜代替传统的晶体管电流镜,使得基准电流产生电路的工作电压减少了一个阈值电压,从而降低灵敏放大器的工作电压.位线电压控制电路中运算放大器的使用减少了由于温度和工艺变化所引起的位线电压变化,进而提高读取操作的精度.采用中芯国际90nm工艺设计,提出的灵敏放大器在1.2V电源电压时的读取时间是14.7ns,相对于传统的结构,单个灵敏放大器的功耗被优化了13%.     

Transient self back-biased buffer for low-voltage high-performanceapplications in standard CMOS technologies

A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer. With only 5% increase in power dissipation     

Simplifying the Design of $SigmaDelta$ Modulators Using FGMOS Transistors

This paper presents the novel design of a second-order continuous-time low-power and low-voltage $SigmaDelta$ modulator. The modulator illustrates a design philosophy based on taking advantage of the extended number of degrees of freedom of the floating-gate MOS transistor. The transistor is simultaneously used to fulfill the following: simplify the topology; accurately implement the modulator coefficients; compensate for gain losses in the integrator and several nonidealities in the comparator; increase the signal range; reduce distortion; shift signal levels according to the specific requirements of individual devices; implement an easy common-mode sensing and feedback strategy; and tune the loop filter and reset the comparator. The modulator operates at 1 V and consumes just over 5 $muhbox{W}$ of power for a signal-to-noise-and-distortion ratio of 60 dB and a maximum bandwidth of 2 kHz, which are typical of many biomedical applications.      

Differential amplifiers that reject common-mode currents

The transistor differential pair is analyzed and it is shown that the common mode rejection ratio is limited both in magnitude and bandwidth by device parameters. The performance is not significantly improved by series common-mode feedback. It is shown that amplifiers with shunt common-mode feedback reject common-mode input currents and that their common-mode rejection ratio can be made independent of device parameters. Applications of such amplifiers include differential operational amplifiers, rejection of large common-mode voltages, and transducer amplifiers. Basic circuitry is described and the performance of a practical circuit is given.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.