基于内存数据库的VLR用户数据处理方法

提出一种对VLR用户数据进行处理的方法,采用面向对象的设计方法并以内存数据库形式设计VLR数据库,通过哈希索引技术将用户数据存储在VLR数据库中.并能对存储在VLR数据库中的移动用户数据进行编辑处理和访问.该方法可快速地进行用户数据的存储和访问,易于设计和实现.并且具有很好的扩展性.     

内存存储模型上的多表连接优化技术研究

分析了面向先进硬件平台上的数据库优化技术,提出了基于内存存储模型的多表连接查询处理优化技术,采用内存存储模型存储维表并对维表主键进行顺序化,从而使维表的主键与内存维表记录的内存偏移地址相一致,实现对维表记录的内存直接访问。通过列存储技术减少维表记录的访问宽度,进一步优化维表访问的cache性能。与基于SQL Server 2005的查询执行计划的连接算法、join index连接算法以及基于列存储模型的优化连接算法进行了实验比较和性能分析,结果表明:基于内存存储模型的多表连接算法在处理星型结构数据仓库多谓词、多连接的复杂查询时具有很好的性能,与join index相比不需要额外的空间开销,与列存储数据模型相比具有更好的兼容性和性能。     

嵌入式系统内存规划方法的研究

内存访问延迟是嵌入式系统性能提高的瓶颈。本文以数据在内存的存储方式为出发点来解决内存访问延迟的问题,并用遗传算法实现了优化算法。     

在应用程序中访问扩展内存的方法及其实现

本文阐述了扩展内存的工作原理和组成方式,并且介绍了LIM开发的EMM对扩展内存管理的原理和工作方式,以及通过在PASCAL的应用程序中对扩展内存进行数据的存入和读取操作,来说明如何对扩展内存进行访问。     

基于高性能I/O技术的Memcached优化研究

内存对象缓存系统在通信方面受制于传统以太网的高延迟,在存储方面受限于服务器内可部署的内存规模,亟需融合新一代高性能I/O技术来提升性能、扩展容量.以广泛应用的Memcached为例,聚焦内存对象缓存系统的数据通路并基于高性能I/O对其进行通信加速与存储扩展.首先,基于日益流行的高性能远程直接内存访问(remote direct memory access, RDMA)语义重新设计通信协议,并针对不同的Memcached操作及消息大小设计不同的策略,降低了通信延迟.其次,利用高性能NVMe SSD来扩展Memcached存储,采用日志结构管理内存与外存2级存储,并通过用户级驱动实现对SSD的直接访问,降低了软件开销.最终,实现了支持JVM环境的高性能缓存系统U2cache.U2cache通过旁路操作系统内核和JVM运行时与内存拷贝、RDMA通信、SSD访问交叠流水的方法,显著降低了数据访问开销.实验结果表明,U2cache通信延迟接近RDMA底层硬件性能;对大消息而言,相较无优化版本,性能提高超过20%;访问SSD中的数据时,相比通过内核I/O软件栈的方式,访问延迟最高降低了31%.     

Alluxio数据随机访问方法的研究

为保证系统的可扩展性和容错性，Alluxio简化了文件系统实现，不支持数据随机访问，但在实际情况中仍有许多应用需要数据随机访问。Alluxio原生Java接口灵活性较差，不支持传统应用，不能完全发挥内存的高速性能。因此在深入分析Alluxio数据读写原理后，提出了新式数据随机访问方法，其核心思想是改变原有数据访问和缓存时机，将对Alluxio中的文件读写转化为对本地内存文件系统的文件读写，从而实现对数据的随机访问。在此基础上，还可以使用内存映射技术进一步提高本地文件的读写性能。测试结果表明，该方法的数据读取性能提升了14.5%，写入性能提升了1.4倍以上。在实际应用场景中合理使用Alluxio及新式数据随机访问方法，可获得数倍至数十倍的性能提升。     

基于Android系统的数据存储访问机制研究

数据存储是开发应用程序时需要解决的最基本的问题,数据必须以某种方式保存,并且能够有效、方便的使用和更新处理。Android系统是基于Google推出的能在智能终端设备上运行的操作系统,随着应用范围和开发需求的增大,对软件的开发效率、性能及数据的存储访问机制受到普遍关注。文中从SharedPreferences、文件、SQLite、ContentProvider、网络五个方面深入阐述了Android系统的数据存储访问机制原理,并结合它们的内在原理,给出了具体实现方法。最后根据它们各自的优缺点,分析了各类存储访问机制的适用范围。     

一种数据级安全访问控制方案

为了更好地保护Web应用系统中敏感数据不被非法访问. 在传统的基于角色的访问控制模型基础上提出了由用户集合和数据访问权限构成的数据访问策略, 并将数据访问策略关联到功能, 通过对原有业务SQL解析, 使用行级访问权限对数据记录进行行级过滤, 再根据列级访问权限对数据记录相应属性进行屏蔽处理来进行数据安全访问控制, 并设计了数据安全访问控制的框架. 最后将该方案应用到新发地农产品供应链管理平台中, 验证了该方案的可行性和有效性.     

一个办公文档类的逻辑文件系统设计

针对当前办公系统所面临的有关海量数据存储和数据访问等若干问题,提出了一个基于数据库的逻辑文件系统的设计方案.该系统不仅能够存储海量数据,还继承了语义文件系统基于内容的访问方式,因而具有了语义访问功能.同时系统将访问方式拓宽到支持内容属性和内容结构的访问.     

RAM（h）模型下SpMV存储访问复杂度的分析

稀疏矩阵向量乘(SpMV)采取压缩行存储格式的算法性能非常差,而寄存器分块算法可以使得数据尽量在靠近处理器的存储层次中访问而提高性能.利用RAM(h)模型进行分析和比较不同算法形式的存储访问复杂度,可以比较两种算法的优劣.通过RAM(h)分析SpMV两种实现形式的存储访问复杂度,同时在奔腾四平台上,测试了7个稀疏矩阵的SpMV性能,并统计了这两种算法中L1,L2,和TLB的缺失率,实验结果与模型分析的数据一致.     

列存储数据库关键技术综述

随着互联网技术的发展、硬件的不断更新、企业及政府信息化的不断深入,应用的复杂性要求越来越高,推动着数据存储技术向着海量数据、分析数据、智能数据的方向发展,以便为数据仓库、在线分析提供高效实时的技术支持。基于行存储的数据库技术面临新的问题,已经出现了技术瓶颈。近些年来,一种新的数据存储理念,即基于列存储的关系型数据库(简称列数据库,下同)应运而生。列数据库能够快速发展,主要原因是其复杂查询效率高,读磁盘少,存储空间少,以及由此带来的技术、管理和应用优势。对列数据库技术的基本现状、关键支撑技术以及应用优势进行了介绍和分析。     

An Efficient Schema Transformation Technique for Data Migration from Relational to Column-Oriented Databases

Data transformation is the core process in migrating database from relational database to NoSQL database such as column-oriented database. However, there is no standard guideline for data transformation from relational database to NoSQL database. A number of schema transformation techniques have been proposed to improve data transformation process and resulted better query processing time when compared to the relational database query processing time. However, these approaches produced redundant tables in the resulted schema that in turn consume large unnecessary storage size and produce high query processing time due to the generated schema with redundant column families in the transformed column-oriented database. In this paper, an efficient data transformation technique from relational database to column-oriented database is proposed. The proposed schema transformation technique is based on the combination of denormalization approach, data access pattern and multiple-nested schema. In order to validate the proposed work, the proposed technique is implemented by transforming data from MySQL database to HBase database. A benchmark transformation technique is also performed in which the query processing time and the storage size are compared. Based on the experimental results, the proposed transformation technique showed significant improvement in terms query processing time and storage space usage due to the reduced number of column families in the column-oriented database.     

A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory

The on-chip memory performance of embedded systems directly affects the system designers＇ decision about how to allocate expensive silicon area. A novel memory architecture, flexible sequential and random access memory （FSRAM）, is investigated for embedded systems. To realize sequential accesses, small “links”are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution is ameliorated by a small sequential access buyer （SAB）. To evaluate the architecture-level performance of FSRAM, we ran the Mediabench benchmark programs on a modified version of the SimpleScalar simulator. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55%, with an average of 9%; furthermore, the FSRAM reduces 53.1% of the data cache miss count on average due to its prefetching effect. We also designed RTL and SPICE models of the FSRAM, which show that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.     

Array Organization in Parallel Memories

The bandwidth mismatch between processor and main memory is one major throughput limiting problem. Although streamed computations have predictable access patterns their references have little temporal locality and are generally too long to cache. A memory and compiler co-optimization aimed at reducing low-level memory accesses using software and hardware locality optimizations is presented. We propose a scalable and predictable parallel memory based on a compiler synthesis of storage schemes for multi-dimensional arrays that are accessed by an arbitrary but known set of data access patterns. Using algebra of non-singular Boolean matrices, we present analysis of conflict-free access to (1) parallel memories, and (2) alignment networks. Finding a multi-pattern storage scheme is one NP-complete problem. An effective compiler heuristic is proposed for finding a storage matrix that minimizes overall memory access time. This applies to arbitrary linear patterns and arbitrary alignment networks. It is shown that the proposed storage scheme finds an optimal storage scheme for parallel (1) FFT, and (2) bitonic sorting. The proposed storage scheme outperforms statically optimized storages in the case of power-of-2 multi-stride access. The case of non power-of-2 strides is also addressed. The performance and scalability of the proposed parallel memory and its predictable access time are presented using numerical and multimedia algorithms. It is shown that a memory utilization above 83% is achieved by our storage scheme for 64 memories, which largely outperforms previous proposals. Our approach provides a tool for matching the storage pattern with the data access patterns needed for embedded systems running streamed computations with predictable data access patterns.     

On Methods to Align and Access Data Arrays in Parallel Computers

We present methods to store and access templates of data arrays in parallel processors with shuffle-exchange-type interconnection networks. For this purpose, we define the class of composite linear permutations. In our method, each element of the data array is stored in the memory module determined by applying a suitable composite linear permutation on its indices. Simple necessary and sufficient criteria to avoid memory conflicts in the access of important templates such as row, column, main diagonal, and square block are given based on the composite linear permutation involved. The criteria so derived also specify the set of permutations to be realized by an interconnection network to avoid network conflicts. In particular, we give the criteria to be satisfied by a scheme of the proposed class to avoid network conflicts during the access of templates, when shuffle-exchange-type networks are used. Almost all the previously known scrambled storage methods are special cases in the class of storage methods presented in this paper.     

近似存储技术综述

随着云计算和物联网业务的快速发展,如何存储爆发式增长的数据成为存储系统的一个巨大挑战.为解决这一问题,近似存储作为一种解决存储资源紧张的必要手段越来越受到关注,它通过利用某些应用程序固有的容错特性,在输出结果的精度和应用的性能间进行权衡,以在满足用户需求的同时提升性能和能效.因此,如何针对不同的存储与应用的特点,通过近似存储数据解决访问性能低、空间开销大和能耗高等问题,已成为存储系统的研究热点.首先介绍近似存储技术的定义与近似区域的识别技术;接着分别阐述适用于高速缓存、内存和外存3个存储层次的近似存储技术,并分析其优缺点与应用范围;最后总结近似存储的特点,并探讨存储系统中近似存储技术的进一步研究方向.     

Block, multistride vector, and FFT accesses in parallel memorysystems

A discussion is presented of the use of dynamic storage schemes to improve parallel memory performance during three important classes of data accesses: vector accesses in which multiple strides are used to access a single vector, block accesses, and constant-geometry FFT accesses. The schemes investigated are based on linear address transformations, also known as XOR schemes. It has been shown that this class of schemes can be implemented more efficiently in hardware and has more flexibility than schemes based on row rotations or other techniques. Several analytical results are shown. These include: quantitative analysis of buffering effects in pipelined memory systems; design rules for storage schemes that provide conflict-free access using multiple strides, blocks, and FFT access patterns; and an analysis of the effects of memory bank cycle time on storage scheme capabilities     

一种支持多种访存技术的CBEA片上多核MPI并行编程模型

现有的CBEA(Cell Broadband Engine Architecture)编程模型多侧重于支持类似于流处理的"批量访存"(Bulk Data Transfer)应用,传统非规则访存应用性能较低.文中基于Cell架构提出了一种同时支持"批量访存"与非规则访存应用的MPI并行编程模型,将通信分解在PPE(PowerPC Processing Element)上,拓宽模型的适用范围;在统一访存接口下,通过运行时访存剖分信息指导选择和优化访存以提高计算效率.实验结果表明,文中提出的编程模型支持多种访存模式并具有很好的并行加速比,可获得较同类相关技术30%~50%左右的性能提升.     

固态存储器短周期存取速度动态控制

由于传统控制方法出现数据误码、存储内存不足问题,导致控制性能变差,为了解决该问题,需对固态存储器短周期存取速度进行动态控制。根据短周期存取速度控制原理,采用均衡加重技术,设计具有针对性的数据传输介质来解决数据误码问题。利用NANDFLASH双平面交替编程的分时加载操作方式,扩大存储内存。使用二级缓存方式对扩大后的内存数据进行缓存读取,根据多线组合指令动态控制缓存读取结果。通过实验结果得出,该方法最低误码率可达到5%,控制性能较好。     

GPU矩阵乘法的性能定量分析模型

性能评价和优化是设计高效率并行程序必不可少的重要工作,存储系统的性能高低直接影响到处理器的整体性能。利用GPGPU-Sim对GPU的存储层次结构进行了模拟,找出了SM数量与存储控制器数量之间最佳配置关系。矩阵乘法是科学计算领域中的基本组成部分,是一种具有计算和访存密集特点的典型应用,其性能是GPU高性能计算的一个重要指标。性能模型作为并行系统性能评价的新的技术解决方案,具有许多其它性能评价方法无法比拟的优势。建立了一个性能模型,模型通过对指令流水线、共享存储器访存、全局存储器访存进行定量分析,找到了程序运行瓶颈,提高了执行速度。实验证明,该模型具有实用性,并有效地实现了矩阵乘法的优化。