A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation

A 28-MHz wideband switched-capacitor (SC) bandpass filter employs an N-path technique and implements transmission zeros in the transfer function to achieve high attenuation. A modified SC biquadratic filter architecture is proposed to achieve high-speed operation. Implemented in a 0.35-/spl mu/m CMOS process, the bandpass filter operates at 28-MHz center frequency with a 3.84-MHz bandwidth and adjacent-channel attenuation of more than 35 dB. At 3-V supply, the filter measures a dynamic range of 37 dB at the 1% THD3 point while dissipating 19.6-mW per pole and occupying a chip area of 1.65 mm/sup 2/.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved     

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

An oversampling bandpass digital-to-analog converter has been designed so as to eliminate the carrier leak and in-band SNR degradation that accompany I and Q channel mismatch in wireless transmitters. The converter combines a cascaded noise-shaping sigma-delta (/spl Sigma//spl Delta/) modulator with digital finite impulse response (FIR) and mixed-signal semi-digital filters that attenuate out-of-band quantization noise. The performance of the converter in the presence of current source mismatch has been improved through the use of bandpass data weighted averaging. An experimental prototype of the converter, integrated in a 0.25-/spl mu/m CMOS technology, provides 83 dB of dynamic range for a 6.25-MHz signal band centered at 50 MHz, and suppresses out-of-band quantization noise by 38 dB.     

Surface Elastic Wave Bandpass Filters for Frequency Synthesis (Short Papers)

Surface elastic wave bandpass filter techniques have been applied to the development of a minaturized frequency synthesizer for satellite communications systems. A bandpass filter centered at 247 MHz has been developed exhibiting less than 7-dB insertion loss over a 6-MHz 1-dB band, with sidelobe rejection greater than 45 dB.     

A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion

A cascade of sigma-delta modulator stages that employ a feedforward architecture to reduce the signal ranges required at the integrator inputs and outputs has been used to implement a broadband, high-resolution oversampling CMOS analog-to-digital converter capable of operating from low-supply voltages. An experimental prototype of the proposed architecture has been integrated in a 0.25-/spl mu/m CMOS technology and operates from an analog supply of only 1.2 V. At a sampling rate of 40 MSamples/sec, it achieves a dynamic range of 96 dB for a 1.25-MHz signal bandwidth. The analog power dissipation is 44 mW.     

New multirate bandpass sigma-delta modulators

A new architecture for fourth- and sixth-order bandpass sigma-delta (BP-SD) modulators is proposed here. The basic BP-SD modulator is obtained from its low-pass (LP) counterpart by means of the standard transformation z/sup -1/ /spl rarr/ -z/sup -2/, which transforms the integrators in the LP modulator into resonators in the BP modulator, and places the input signal band at the frequency f/sub s//4, where f/sub s/ is the sampling rate. In the proposed architecture, the second resonator (and the third one for the sixth-order case) is implemented using a two-path strategy, by means of two high-pass filters (whose poles are located at f/sub s//2) operating in a time-interleaved mode. However, unlike other BP-SD modulators using the two-path strategy, in our approach, the effective sampling frequency in the second resonator (and in the third one for the sixth-order case) is increased to 2/spl middot/f/sub s/ by maintaining the clock rate of the high-pass filters to f/sub s/ which, in turn, places their poles at f/sub s//2. The signal band in the input of the second resonator is moved from the center frequency f/sub s//4 to f/sub s//2 by a modulation process that separates the signal into their in-phase and quadrature components. Another demodulation process in the digital domain reverses this frequency translation of the signal band before the output signal is converted to the analog domain and fed back to the modulator input. A detailed theoretical analysis of the architecture is done in the paper. Owing to the multirate nature of the proposed modulators, simulation results show an improvement of approximately 12 dB in the input dynamic range (fourth-order case) when compared to conventional modulators of the same order clocked at the same frequency rate (in the first resonator).     

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.     

An 81-MHz IF receiver in CMOS

An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass ΣΔ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass ΣΔ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-μm CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power     

Bandpass Sigma–Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with G_m-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution     

A double-sampling pseudo-two-path bandpass ΔΣ modulator

A double-sampling pseudo-two-path bandpass ΔΣ modulator is proposed. This modulator has an output rate equal to twice the clock rate, uses n/2 operational amplifiers (op-amps) for an nth-older noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass ΔΣ modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively     

A two-path bandpass ΣΔ modulator for digital IFextraction at 20 MHz

Oversampled bandpass A/D converters based on sigma-delta (ΣΔ) modulation can be used to robustly digitize the types of narrowband intermediate frequency (IF) signals that arise in radios and cellular systems. This paper proposes a two-path architecture for a fourth-order, bandpass modulator that is more tolerant of analog circuit limitations at high sampling speeds than conventional implementations based on the use of switched-capacitor biquadratic filters. An experimental prototype employing the two-path topology has been integrated in a 0.6-μm, single-poly, triple-metal CMOS technology with capacitors synthesized from a stacked metal structure. Two interleaved paths clocked at 40 MHz digitize a 200-kHz bandwidth signal centered at 20 MHz with 75 dB of dynamic range while suppressing the undesired mirror image signal by 42 dB. At low input signal levels, the mixing of spurious tones at DC and f_s/2 with the input appears to degrade the performance of the modulator; out-of-band sinusoidal dither is shown to be an effective means of avoiding this degradation. The experimental modulator dissipates 72 mW from a 3.3 V supply     

A 63 dB SNR, 75-mW Bandpass RF Σ∆ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-μm SiGe BiCMOS Technology

A fourth-order continuous-time LC bandpass sigma-delta ADC is designed using a new architecture with only non-return-to-zero feedback DACs to mitigate problems associated with clock jitter, along with individual control of coefficients in the noise transfer function. The ADC performs direct digitization of RF signals around 950-MHz center frequency with a 3.8-GHz clock. The operation of the proposed ADC architecture is examined in detail and extra design parameters are introduced to enhance the operating range and improve the stability of the ADC. Measurement results of the ADC, implemented in IBM 0.25-mum SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz, while consuming 75 mW of power from plusmn1.25-V supply     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver

A bandpass delta-sigma modulator (BPDSM) is a key building block to implement a digital intermediate frequency (IF) receiver in a wireless communication system. This paper proposes a time-interleaved (TI) recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver. The proposed TI BPDSM provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach. The test chip was designed and fabricated for a 30-MHz IF system with a 0.35-/spl mu/m CMOS process. The measured peak SNR for a 1.25-MHz bandwidth is 48 dB while dissipating 75 mW from a 3.3-V supply and occupying 1.3 mm/sup 2/.     

A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.     

The design of a 3-V 900-MHz CMOS bandpass amplifier

A new bandpass amplifier which performs both functions of low-noise amplifier (LNA) and bandpass filter (BPF) is proposed for the application of 900-MHz RF front-end in wireless receivers. In the proposed amplifier, the positive-feedback Q-enhancement technique is used to overcome the low-gain low-Q characteristics of the CMOS tuned amplifier. The Miller-capacitance tuning scheme is used to compensate for the process variations of center frequency. Using the high-Q bandpass amplifier in the receivers, the conventional bulky off-chip filter is not required. An experimental chip fabricated by 0.8-μm N-well double-poly-double-metal CMOS technology occupies 2.6×2.0 mm² chip area. Under a 3 V supply voltage, the measured quality factor is tunable between 2.2 and 44. When the quality factor is tuned at Q=30, the measured center frequency of the amplifier is tunable between 869-893 MHz with power gain 17 dB, noise figure 6.0 dB, output 1 dB compression point at -30 dBm, third-order input intercept point at -14 dBm, and power dissipation 78 mW     

Low-distortion bandpass /spl Sigma/-/spl Delta/ modulator for wireless radio receivers

A low-distortion bandpass sigma-delta modulator is proposed. It was found that the key to improving linearity is to add a feedforward signal path in a double-delay resonator bandpass structure. The proposed technique improves the tonal behaviour even at low oversampling ratio and can be applied for any order of modulator. Based on the proposed architecture, a fourth-order single-bit sigma-delta modulator can achieve a dynamic range of 84 dB and a spurious free dynamic range of 98 dB at 10.71 MHz with a signal bandwidth of 200 kHz, making it ideal for a narrowband IF-sampled wireless receiver designed for compliance with GSM/GPRS standards.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

Calibration study of dual-band Weaver–Hartley receiver architecture

This paper presents a calibration study of dual-band image rejection receiver based on combined Weaver–Hartley architecture, with improved image rejection of first and second image signals. The system implementation is based on dual-band WLAN 802.11 a/g. When the desired signal is at 5.7-GHz band, the 2.4-GHz band becomes the first image signal and vice versa. The output IF frequency is at 30-MHz. The detection of the gain and phase mismatches is based on modeling, extraction of related error signals and correcting them in closed loop. Moreover, we demonstrate an open loop technique to reach the phase and gain correction signals. The correction signals can be digitally stored and applied as digital trimming control on the LO signals. Simulation showed close to 60 dB of image rejection ratio for the first image signal. Second image signal is rejected by a 4-section poly-phase filter.