On adaptive experiments for nondeterministic finite state machines

Adaptive experiments are well defined in the context of finite state machine (FSM) based analysis, in particular, in FSM based testing where homing and distinguishing experiments with FSMs are used for test derivation. In this paper, we define and propose algorithms for deriving adaptive homing and distinguishing experiments for non-initialized nondeterministic finite state machines (NFSMs). For NFSMs, the construction of adaptive experiments is rather complex as the partition over produced outputs does not define a partition over the set of states but a collection of intersecting subsets, and thus, the refinement of such set system is more difficult than the refinement of a partition. Given a complete non-initialized possibly non-observable NFSM, we establish necessary and sufficient conditions for having adaptive homing and distinguishing experiments and evaluate the height of these experiments.     

Reducing the Use of Resources in the FPGA Circuit of a Moore FSM

Two modifications of coding states of a Moore finite-state machine (FSM) are proposed. The modifications are based on pseudoequivalent states of the machine with a view to reducing the number of rows in the transition table of the machine and also on the use of free embedded memory blocks in implementing a system of microoperations. Synthesis methods for Moore FSMs are proposed. Research results are presented and appropriate application areas of the proposed methods are specified.     

Synthesis of finite state machines for improved state verification

Finite State Machines (FSMs) are used in diverse areas to model hardware and software systems. Verification of FSMs is essential to ensure reliability of systems. To verify that a machine is in an expected state in testing, Unique Input/Output (UIO) sequences are used. The aforementioned testing methodology requires that each state in the FSM has an UIO. However, it is possible for a given machine that few or even none of its states have an UIO sequence. This paper presents a guided heuristic algorithm for synthesizing FSMs such that each state has an UIO sequence. The states of an FSM with identical I/O labels on transitions are grouped in order to identify the states which do not possess UIO sequence. The transitions are then augmented by adding extra output terminals incrementally so that new UIO sequences are created for the states. A greedy approach is used to optimize the number of added outputs. Initially, the transitions which lead to state convergence (i.e., transitions with identical input/output labels taking a set of states to the same next state) and constrained self-loop (i.e., transitions taking a set of states either to itself or leads to state convergence) are identified since a state with only these transitions will never have a UIO sequence. Extra output terminals are added to the FSM which are used only while testing and the augmented output labels make sure that the states are neither convergent nor has constrained self-loop, thereby ensuring UIO sequence. The proposed algorithm, referred to as AUGP, was tested with a large number of FSMs including the Microelectronics Center of North Carolina (MCNC) FSM benchmarks. The augmented state transition table was used as input to a UIO computation algorithm (developed by the same authors [Ahmad I, et al. IEE Proc Comput Digital Tech 2004;151(2):131]) to check the performance of the augmentation algorithm and the tested FSMs were found to possess UIO sequence for all states.     

Effective algorithms for constructing minimum cost adaptive distinguishing sequences

Context: Given a Finite State Machine (FSM), a checking sequence is a test sequence that determines whether the system under test is correct as long as certain standard assumptions hold. Many checking sequence generation methods use an adaptive distinguishing sequence (ADS), which is an experiment that distinguishes the states of the specification machine. Furthermore, it has been shown that the use of shorter ADSs yields shorter checking sequences. It is also known, on the other hand, that constructing a minimum cost ADS is an NP-hard problem and it is NP-hard to approximate. This motivates studying and investigating effective ADS construction methods.Objective: The main objective of this paper is to suggest new methods that can compute compact ADSs to be used in the construction of checking sequences.Method: We briefly present the existing ADS construction algorithms. We then propose generalizations of these approaches with a set of heuristics. We also conduct experiments to compare the size of the resultant ADSs and the length of the checking sequences constructed using these ADSs.Results: The results indicate that when the ADSs are constructed with the proposed methods, the length of the checking sequences may reduce up to 54% (40% on the average).Conclusions: In this paper, we present the state of the art ADS construction methods for FSMs and we propose generalizations of these methods. We show that our methods are effective in terms of computation time and ADS quality.     

使用概率规则文法评估人机界面可用性

提出一种在界面系统设计规约的基础上使用的可用性评估方法.首先使用有限状态自动机抽象界面系统设计,根据概率规则文法对有限状态自动机的状态转换概率进行预测;然后结合用户的熟练程度提出了界面可用性评估算法;最后讨论了一个手机界面的可用性计算实例.文中方法能够在界面系统生命周期的早期使用,以较早地对不同设计方案进行比较,降低开发风险.     

Sequential algorithm for low-power encoding internal states of finite state machines

A heuristic method for encoding internal states (state assignment) of finite state machines (FSMs) so as to reduce their power consumption is proposed. A feature of the proposed approach is that the state assignment procedure takes into account the activity function of the memory elements when the FSM transits from a current state to other states that have already been encoded. A procedure for determining the power consumption of the FSM based on the codes of its internal states and probabilities of appearance of units at each input of the FSM is described. Experiments showed that the proposed approach makes it possible to reduce the power consumption of the FSM by 39% on the average compared with the NOVA algorithm and sometimes by 68%. In conclusion, the possibilities of improving the performance of the proposed algorithm in the synthesis of a specific FSM are discussed and promising directions of further research are indicated.     

一种输电线路巡检机器人越障规划方法

针对输电线路巡检机器人的局部自主与远程控制方式,提出了一种基于有限状态机的越障规划方法.将巡检机器人的越障运动过程分解成若干离散化的关键状态,建立了运动规划的有限状态机模型.采用一种基于模糊方法的产生式系统用于推理越障模式,并产生运动序列.仿真与现场实验验证了越障规划方法的正确性和有效性,该方法可应用于输电线路巡检机器人运动控制.     

Separating sequence overlap for automated test sequence generation

Finite state machines have been used to model a number of classes of system and there has thus been much interest in the automatic generation of test sequences from finite state machines. Many finite state machine based test techniques utilize sequences that check the final states of transitions, the most general such sequence being a separating sequence: an input sequence that distinguishes between two states of an FSM. When using such techniques the test sequence length can be reduced by utilizing overlap. This paper investigates overlap for separating sequences and shows how this can be incorporated into test sequence generation.     

Minimization of mealy finite-state machines by using the values of the output variables for state assignment

Structural models of finite-state machines (FSMs) that make it possible to use the values of the output variables for encoding the internal states are studied. To minimize the area (the parameter area is used to denote cost in the context of this paper) of FSM implementation, it is proposed to use the structural model of the class D FSM. A method for the design of the class D FSM in FPGA is proposed. This method involves two phases—splitting the internal states of the FSM (to satisfy the necessary conditions for the construction of the class D FSM) and encoding the internal states (to ensure that the codes are mutually orthogonal). It is shown that the proposed method reduces the area of FSM implementation for all families of FPGAs of various manufacturers by a factor of 1.41–1.72 on average and by a factor of two for certain families. Practical issues concerning the method and the specific features of its use are discussed, and possible directions of the elaboration of this approach are proposed.     

FSM状态间逻辑条件检验的算法研究

有限状态机(FSM)是VLSI控制结构的一种映射,它的自动综合成为设计自动化的一个十分重要的环节和途径。本文讨论在FSM自动综合中输入阶段的状态间逻辑条件检验的问题,研究分析状态间逻辑条件检验的相互关系及影响,并提出了FSM状态间逻辑条件检验的优化算法,从而使时间复杂度降低,实现更加简便。最后,本文给出了优化算法的流程和一些实验结果,结果令人满意。     

Transformation of a mealy finite-state machine into a moore finite-state machine by splitting internal states

The problem of transformation of a Mealy finite-state machine (FSM) into an equivalent Moore FSM is considered. This problem often arises in the practice of engineering design, when one needs to avoid direct dependence of the output values on variations in the input values. The proposed approach uses the operation of splitting of internal states of an FSM and represents the machine as a list of transitions. Experiment results have shown that transformation of Mealy FSM into Moore FSM increases the number of internal states, on the average, by a factor of 1.96 and increases the number of transitions by a factor of 2.05; the cost of realization of Moore FSM using an industrial software package is approximately twice as great as the corresponding cost for a Mealy machine. The up-to-date tendencies of development of minimization methods and Moore FSM synthesis are described.     

Road network extraction: a neural-dynamic framework based on deep learning and a finite state machine

Extracting road networks from very-high-resolution (VHR) aerial and satellite imagery has been a long-standing problem. In this article, a neural-dynamic tracking framework is proposed to extract road networks based on deep convolutional neural networks (DNN) and a finite state machine (FSM). Inspired by autonomous mobile systems, the authors train a DNN to recognize the pattern of input data, which is an image patch extracted in a detection window centred at the current location of the tracker. The pattern is predefined according to the environment and associated with the states in the FSM. A vector-guided sampling method is proposed to generate the training data set for the DNN, which extracts massive image-direction pairs from the imagery and existing vector road maps. In the tracking procedure, the size of the detection window is determined by a fusion strategy and the extracted image patches represent the orientation features of the road (local environment) that can be recognized by the trained DNN. The reactive unit in FSM associates states with behaviours of the tracker while continually modifying the orientation to follow the road and generating a sequence of states and locations. In this way, our framework combines the DNN and FSM. DNN acts as a key component to recognize patterns from a complex and changing environment; FSM translates the recognized patterns to states and controls the behaviour of the tracker. The results illustrate that our approach is more accurate and efficient than the traditional ones.     

基于规范的移动Ad Hoc网络分布式入侵检测

移动ad hoc网络是移动节点自组织形成的网络,由于其动态拓扑、无线传输的特点,容易遭受各种网络攻击。传统的网络安全措施,如防火墙、加密、认证等技术,在移动ad hoc网络中难以应用,因此提出一种基于有限状态机分布式合作的入侵检测算法。首先,将整个网络分为子区域,每一区域随机选出簇头担任监视节点,负责本区域的入侵检测。其次,按照DSR路由协议构筑节点正常行为和入侵行为的有限状态机,监视节点收集其邻居节点的行为信息,利用有限状态机分析节点的行为,发现入侵者。本算法不需要事先进行数据训练并能够实时检测入侵行为。最后,通过模拟实验证实了算法的有效性。     

Canonical finite state machines for distributed systems

There has been much interest in testing from finite state machines (FSMs) as a result of their suitability for modelling or specifying state-based systems. Where there are multiple ports/interfaces a multi-port FSM is used and in testing, a tester is placed at each port. If the testers cannot communicate with one another directly and there is no global clock then we are testing in the distributed test architecture. It is known that the use of the distributed test architecture can affect the power of testing and recent work has characterised this in terms of local s-equivalence: in the distributed test architecture we can distinguish two FSMs, such as an implementation and a specification, if and only if they are not locally s-equivalent. However, there may be many FSMs that are locally s-equivalent to a given FSM and the nature of these FSMs has not been explored. This paper examines the set of FSMs that are locally s-equivalent to a given FSM M. It shows that there is a unique smallest FSM χ_min(M) and a unique largest FSM χ_max(M) that are locally s-equivalent to M. Here smallest and largest refer to the set of traces defined by an FSM and thus to its semantics. We also show that for a given FSM M the set of FSMs that are locally s-equivalent to M defines a bounded lattice. Finally, we define an FSM that, amongst all FSMs locally s-equivalent to M, has fewest states. We thus give three alternative canonical FSMs that are locally s-equivalent to an FSM M: one that defines the smallest set of traces, one that defines the largest set of traces, and one with fewest states. All three provide valuable information and the first two can be produced in time that is polynomial in terms of the number of states of M. We prove that the problem of finding an s-equivalent FSM with fewest states is NP-hard in general but can be solved in polynomial time for the special case where there are two ports.     

机床控制流程的一种有限状态机表达方法

面向过程的IEC-1131-3规范已难以满足机床 控制流程表达新的应用需求,为了更好地支持控制器开放式体系结构设计和面向对象系统实 现技术,我们扩展了有限状态机的基本概念,提出了一种机床控制流程表达的分层式有限状 态机(FSM)方法．本文首先对分层式FSM的组织方法、特性、形式定义等进行了详细讨论;为 了进一步阐明这种方法的表达特性,我们介绍了一种分层式FSM表达的机床控制器总体结构 ,并讨论了这种结构下的开放性设计表达和系统实现等相关问题．     

Exploring alternatives for transition verification

When an implementation under test (IUT) is state-based, and its expected abstract behavior is given in terms of a finite state machine (FSM), a checking sequence generated from a specification FSM and applied to an IUT for testing can provide us with high-level confidence in the correct functional behavior of our implementation. One of the issues here is to generate efficient checking sequences in terms of their lengths. As a major characteristics, a checking sequence must contain all β-sequences for transition verification. In this paper, we discuss the possibility of reducing the lengths of checking sequences by making use of the invertible transitions in the specification FSM to increase the choice of β-sequences to be considered for checking sequence generation. We present a sufficient condition for adopting alternative β-sequences and illustrate typical ways of incorporating these alternative β-sequences into existing methods for checking sequence generation to reduce the lengths. Compared to the direct use of three existing methods, our experiments show that most of the time the saving gained by adopting alternative β-sequences falls in the range of 10–40%.     

基于同步有向图的同步测试序列生成方法

使用多测试单元的测试系统可以对多端口协议实现进行一致性测试，但是在进行这种一致性测试时，测试系统各个端口之间可能会出现同步问题，现在，解决同步问题常用的办法是在测试单元相应端口之间增加同步连接，然后通过此同步连接相互发送同步消息来进行同步，多端口协议和其它类型的分布式系统可以用有限状态机模型来描述，目前，同步问题被分为双端口同步问题，多端口同步问题，紧同步问题等多种类型，该文考虑两种有限状态机测试问题，第一种是面向端口的测试，不考虑有限状态机测试单元之间的通信问题，第二种面向组的测试，有限状态机中的各个端口被分成互不相关的多个组，属于不同组中的测试单元之间互不通信，该文提出了一种基于同步有向图的同步测试序列生成方法，这种生成方法适用于Pair同步，Port同步和组同步问题，并且，这种方法也可以用来判断如何在非同步测试序列中增加同步通信，将非同步测试序列转化为同步测试序列。     

Large aligned treebanks for syntax-based machine translation

We present a collection of parallel treebanks that have been automatically aligned on both the terminal and the non-terminal constituent level for use in syntax-based machine translation. We describe how they were constructed and applied to a syntax- and example-based machine translation system called Parse and Corpus-Based Machine Translation (PaCo-MT). For the language pair Dutch to English, we present non-terminal alignment evaluation scores for a variety of tree alignment approaches. Finally, based on the parallel treebanks created by these approaches, we evaluate the MT system itself and compare the scores with those of Moses, a current state-of-the-art statistical MT system, when trained on the same data.     

A method for minimizing Moore finite-state machines by merging two states

The problem of minimization of Moore finite-state machines (FSMs) is considered. This problem often arises in designing digital devices based on programmable logic devices. The proposed approach uses the operation of merging of two states of an FSM and the representation of the FSM as a list of transitions. Conditions guaranteeing the identical operation and deterministic behavior of the transformed FSM obtained by merging two states are given. The cases when wait states can emerge are also discussed. Algorithms for minimizing the number of internal states, transition paths, and the number input variables of Moore FSMs are described. Experimental results have shown that the proposed approach reduces the number of internal states by 6% on the average and sometimes by a factor of 1.86; the number of transitions is reduced by 20% on the average and sometimes by a factor of 2.83. The use of the proposed method in combination with the STAMINA computer program reduces the number of internal states by 16% on the average and sometimes by a factor of 2.17; the number of transitions is reduced by 41% on the average and sometimes by a factor of 7.97. In conclusion, important directions of research concerning the minimization of FSMs are discussed.     

Enhancing performance of failure-prone clusters by adaptive provisioning of cloud resources

In this paper, we investigate Cloud computing resource provisioning to extend the computing capacity of local clusters in the presence of failures. We consider three steps in the resource provisioning including resource brokering, dispatch sequences, and scheduling. The proposed brokering strategy is based on the stochastic analysis of routing in distributed parallel queues and takes into account the response time of the Cloud provider and the local cluster while considering computing cost of both sides. Moreover, we propose dispatching with probabilistic and deterministic sequences to redirect requests to the resource providers. We also incorporate checkpointing in some well-known scheduling algorithms to provide a fault-tolerant environment. We propose two cost-aware and failure-aware provisioning policies that can be utilized by an organization that operates a cluster managed by virtual machine technology, and seeks to use resources from a public Cloud provider. Simulation results demonstrate that the proposed policies improve the response time of users’ requests by a factor of 4.10 under a moderate load with a limited cost on a public Cloud.