Theory of MNOS memory transistor

A theory on the switching behavior of the metal-Si3N4-SiO2-semiconductor (MNOS) memory transistor is presented which is consistent with the experimentally observed facts. The theory treats the switching process as being initially predominantly direct band-to-band tunneling and then dominated by modified-Fowler-Nordheim tunneling. The large-signal mathematical treatment includes both of these tunneling terms. The resultant charge-transport equation is rather complex; a numerical method is needed to obtain an exact solution, However, a grossly approximate closed-form solution has been obtained, which indicates that the transferred charge is initially a linear function of time and then logarithmic. This is similar to many of the previous theories. However, the coefficients in the current and charge solutions of the present theory contain the essential material, device, and operating parameters which are absent in previous theories. This makes the present model readily usable as a guide in the design and optimization of MNOS devices.     

Floating-gate nanofibrous electret arrays for high performance nonvolatile organic transistor memory devices

Nanofibrous electret arrays based organic field-effect floating-gate transistor memory was firstly developed by electrospinning. The nanofiber arrays are composed of a novel porphyrin molecule of [5,15-bis[4-(pyridyl)ethynyl]-10,20-diphenyl]-21H,23H-porphyrin (DPP) as charge-trapping elements and polystyrene (PS) as the tunneling layer. The floating-gate transistor memory based on electrospinning nanofibrous electret arrays exhibited a reliable controllable threshold voltage shift and effective charge-trapping ability which was obviously superior to the counterparts fabricated with widely employed spin-coating technique. The result shows that electrospinning can be used as an effective artificial strategy to produce predesigned microstructure for the electrets, optimize the electrical memory characteristics, and may be applied in future nonwoven electronic memory devices.     

Low-power bipolar transistor memory cells

Low- and high-barrier Schottky diodes have been combined with bipolar transistors to produce planar integrated-circuit low-area memory cells that hold at 75 /spl mu/W. Low-barrier diodes formed on p-type ion-implanted silicon (10/SUP 17/ cm/SUP -3/) are used as high-resistance collector loads. High-barrier diodes formed on n-type epitaxial silicon (10/SUP 16/ cm/SUP -3/) provide low-capacitance low-leakage coupling to digit lines in a memory array. The highly reproducible rhodium silicide on silicon Schottky diodes, as well as high-quality ohmic contacts, are formed in one sequence of sputtering and high-temperature operations. The process is fully compatible with beam-lead technology. It is estimated that a 512-word memory module using these cells would operate at a 60-ns READ or WRITE cycle time.     

Memory operations of 1T2C-type ferroelectric memory cell withexcellent data retention characteristics

A novel FET-type ferroelectric memory cell with one-transistor, and two-capacitor (1T2C) structure was fabricated and characterized, in which the generation of depolarization field in ferroelectric film during data retention was suppressed by polarizing two ferroelectric capacitors in opposite directions. It was demonstrated that the stored data were nondestructively read-out and their retention time was much longer than that of conventional ferroelectric-gate FET     

Diamond transistor performance and fabrication

The author reviews some of the device properties of diamonds, as well as recently developed diamond device fabrication techniques for high-frequency, high-power transistors. Two advantages of diamond over other semiconductors used for high-frequency, high power devices are its high thermal conductivity and high electric-field breakdown. Homoepitaxial diamond has been grown by both plasma and hot-filament techniques. The device properties of homoepitaxial diamond produced by the hot-filament technique are reviewed. Much of the development necessary for the production of diamond devices already exists. Doping by homoepitaxy, diamond etching, device quality SiO₂-diamond interface, and ohmic contact technology are reviewed. The remaining problems are the development of large area single crystal diamond substrates, improvement of doping techniques, and refinement in ohmic contact technology     

Coulomb blockade memory using integrated single-electron transistor/metal-oxide-semiconductor transistor gain cells

A 3/spl times/3-bit Coulomb blockade memory cell array has been fabricated in silicon-on-insulator (SOI) material. In each cell, the Coulomb blockade effect in a single-electron transistor is used to define two charge states. The charge is stored on a memory node of area 1 /spl mu/m/spl times/1 /spl mu/m or 1 /spl mu/m/spl times/70 nm and is sensed with gain by a metal-oxide-semiconductor transistor. The write/read operation for a selected cell within the array is demonstrated. The measured states are separated by /spl sim/1000 electrons for the 1 /spl mu/m/spl times/1 /spl mu/m memory node cell and by 60 electrons for the 1 /spl mu/m/spl times/70 nm memory node cell. Single-electron transistor controlled operation persists up to a temperature of 65 K.     

Ferroelectric transistor memory arrays on flexible foils

In this paper, we successfully fabricated and operated passive matrix P(VDF–TrFE) transistor arrays, i.e. memory arrays in which no pass-transistors or other additional electronic components are used. Because of the smaller cell, a higher integration density is possible. We demonstrate arrays up to a size of 16 × 16, processed on thin (25 μm) poly(ethylene naphthalate) substrates, using Indium–Gallium–Zinc–Oxide (IGZO) as the semiconductor and 200 nm-thick P(VDF–TrFE) as a ferroelectric gate dielectric. The memory transistors have remnant current modulations of ～10⁵ with a retention time of more than 12 days. They can be switched in less than 1 μs at operating voltages of 25 V. Switching speed is strongly decreased with decreasing voltage: at ～10 V the transistors do not switch within 10 s. This difference in switching speed of more than 4 orders in magnitude when changing the electric field by a factor of only 2.5 makes these memories robust towards disturb voltages, and forms the basis of integration of these transistors in passive matrix-addressable transistor arrays that contains only one (memory) transistor per cell. It is shown that with current technology and memory characteristics it is possible to scale up the array size in the future.     

High speed and high density static induction transistor memory

Describes a high speed and high density dynamic RAM utilizing a static induction transistor (SIT) structure. The main conduction mechanism of an SIT is carrier injection control due to the potential hump at the intrinsic gate, where the potential hump is capacitively controlled by the gate and the drain voltage in a basic operation. The SIT forms a dynamic RAM memory cell if one of the drain and the source regions is set as a floating region directly connected to the storage capacitor. Basic operation of a single SIT memory cell is experimentally demonstrated in this paper.     

High-frequency performance of diamond field-effect transistor

The microwave performance of a diamond metal-semiconductor field-effect transistor (MESFET) is reported for the first time. MESFETs with a gate length of 2-3 μm and a source-gate spacing of 0.1 μm were fabricated on the hydrogen-terminated surface of an undoped diamond film grown by microwave plasma chemical vapor deposition (CVD) utilizing a self-aligned gate fabrication process. A maximum transconductance of 70 mS/mm was obtained on a 2 μm gate MESFET at V_GS=-1.5 V and V_DS=-5 V,for which a cutoff frequency f_T and a maximum oscillating frequency f_max of 2.2 GHz and 7 GHz were obtained, respectively     

Bipolar transistor selected P-channel flash memory cell technology

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory     

A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor

The ferroelectric field effect has successfully been demonstrated on a bulk semiconductor (silicon) using a thin ferroelectric film of bismuth titanate (Bi4Ti3O12) deposited onto it by RF sputtering. A new memory device, the metal-ferroelectric-semiconductor transistor (MFST); has been fabricated. This device utilizes the remanent polarization of a ferroeletric thin film to control the surface conductivity of a bulk semiconductor substrate and perform a memory function. The capacitance-voltage characteristics of the metal-ferroelectric-semiconductor structure were employed to study the memory behavior. The details of the study together with a preliminary results on the MFST are presented.     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Operation of single transistor type ferroelectric random access memory

Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the 1T type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.     

Engineering of nitrogen profile in an ultrathin gate insulator to improve transistor performance and NBTI

During evaluation of negative bias temperature instability (NBTI) in short-channel devices, we found that using an optimized nitrogen depth profile is important in suppressing NBTI when scaling down CMOS devices. Performing the NO anneal process before oxidation yeilds good transistor performance, suppressing NBTI by 25%. When using more nitrogen to moderate gate leakage and boron penetration, in addition to the amount of nitrogen, it is important to control the depth profile of the nitrogen on the gate insulator, as our research shows that the interface peak concentration of nitrogen enhances NBTI degradation.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Low-voltage programmable/erasable high performance flexible organic transistor nonvolatile memory based on a tetratetracontane passivated ferroelectric terpolymer

Future flexible electronic systems require memory devices combining low power consumption and mechanical bendability. However, high programming/erasing (P/E) voltages, which are universally required to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a novel route to achieve a low-voltage programmable/erasable flexible Fe-OFET NVM. Ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)], rather than the conventional ferroelectric copolymer poly(vinylidene-fluoride-trifluoroethylene) [P(VDF-TrFE)], is used as the gate dielectric. The low coercive field of P(VDF-TrFE-CTFE) is the main contribution to the low-voltage operation in the Fe-OFET NVM, even with a relative thick ferroelectric gate dielectric layer. By depositing a long-chain alkane molecule Tetratetracontane (TTC) as the passivation layer on the surface of P(VDF-TrFE-CTFE) film, the layer-by-layer growth mode of semiconductor pentacene is obtained, which results in a large crystalline grain and good interface morphology at the channel/dielectric. Therefore, the mobility of Fe-OFET NVMs is greatly improved. As a result, a high performance flexible Fe-OFET NVM is achieved, with a low P/E voltage of ±15 V, high mobility up to 0.5 cm² V⁻¹ s⁻¹, reliable P/E endurance property over 1000 cycles, stable data storage retention capability over 6000 s, and excellent mechanical bending durability without visible degradation after 2000 repetitive tensile bending cycles at a small curvature radius of 4.0 mm.     

Device modeling of ferroelectric memory field-effect transistor (FeMFET)

A numerical analysis of the electrical characteristics for the ferroelectric memory field-effect transistors (FeMFETs) is presented. Two important structures such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMISFET) are considered. A new analytic expression for the relation of polarization versus electric field (P-E) is proposed to describe the nonsaturated hysteresis loop of the ferroelectric material. In order to provide a more accurate simulation, we incorporate the combined effects of the nonsaturated polarization of ferroelectric layers and the nonuniform distributions of electric field and charge along the channel. We also discuss the possible nonideal effects due to the fixed charges, charge injection, and short channel. The present theoretical work provides some new design rules for improving the performance of FeMFETs.     

Optimizing polysilicon thin-film transistor performance withchemical-mechanical polishing and hydrogenation

Chemical-mechanical polishing and hydrogen passivation were jointly used to improve the electrical characteristics of polycrystalline-Si thin-film transistors (poly-Si TFT's). It was found that each treatment affects the devices differently; polishing is more effective in smoothing the poly-Si/SiO₂ interface while hydrogenation is more effective in passivating the grain boundaries. Their effects are additive. Hence, optimal device performance was achieved by combining both treatments