Strained ${rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance

A novel-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors was demonstrated. The additional SiGe structure couples additional strain from the S/D stressors to the overlying Si channel, leading to enhanced strain effects in the channel region. We termed the SiGe region a strain-transfer structure due to its role in enhancing the transfer of strain from lattice-mismatched S/D stressors to the channel region. Numerical simulations were performed using the finite-element method to explain the strain-transfer mechanism. A significant drive current I_DSAT improvement of 40% was achieved over the unstrained control devices, which is predominantly due to the strain-induced mobility enhancement. In addition, the impact of scaling the device design parameters on transistor drive current performance was investigated. Guidelines on further performance optimization in such a new device structure are provided.     

Design of Si/SiGe heterojunction complementarymetal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si_0.7Ge _0.3 buffer, a strained Si quantum well (the electron channel), and a strained S_1-xGe_x (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-μm channel length generation     

A deep submicron Si1-xGex/Si vertical PMOSFETfabricated by Ge ion implantation

We report a deep submicron vertical PMOS transistor using strained Si_1-xGe_x channel formed by Ge ion implantation and solid phase epitaxy. These vertical structure Si_1-xGe_x /Si transistors can be fabricated with channel lengths below 0.2 μm without using any sophisticated lithographic techniques and with a regular MOS process. The enhancement of hole mobility in a direction normal to the growth plane of strained Si_1-xGe_x over that of bulk Si has been experimentally demonstrated for the first time using this vertical MOSFET. The drain current of these vertical MOS devices has been found to be enhanced by as much as 100% over control Si devices. The presence of the built-in electric field due to a graded SiGe channel has also been found to be effective in further enhancement of the drive current in implanted-channel MOSFET's     

SiGe heterostructure field-effect transistor using V-shaped confining potential well

A working p-type SiGe heterostructure field-effect transistor, utilizing a V-shaped confining potential well as the conducting channel, has been successfully fabricated. The upper boron /spl delta/-doping layer acts as a diffusion barrier to slow diffusion into the undoped Si cap layer. On the other hand, the bottom boron /spl delta/-doping layer prevents hot holes from escaping the channel by improving carrier confinement. It is found that when a V-shaped confining potential well is used as the conducting channel, the devices exhibit the excellent property not only of higher current density but also enhancement in extrinsic transconductance and linear operation range over a wider dynamic range than those of /spl delta/-doped devices for the same dose in SiGe conducting well. The measured transconductance is enhanced three to six times over that of the other /spl delta/ cases.     

Numerical Study of Flicker Noise in p-Type $ hbox{Si}_{0.7}hbox{Ge}_{0.3}/hbox{Si}$ Heterostructure MOSFETs

Device-level simulation capabilities have been developed to investigate low-frequency noise behavior in p-type Si_0.7Ge_0.3/Si heterostructure MOS (SiGe p-HMOS) transistors. The numerical model is based on the impedance field method; it accounts for a trap-induced carrier number fluctuation, a layer-dependent correlated mobility fluctuation, and a Hooge mobility fluctuation in the buried and parasitic surface channels, respectively. Simulations based on such models have been conducted for SiGe p-HMOS transistors, and the results have been carefully correlated with experimental data. Quantitative agreement has been obtained in terms of the noise level dependence on gate biases, drain currents, and body biases, revealing the important role of the dual channels in the low-frequency noise behavior of SiGe p-HMOS devices.     

Fabrication and application of MOS-HBT-NDR circuit using standard SiGe process

A novel negative differential resistance (NDR) circuit made of a metal-oxide-semiconductor field-effect-transistor (MOS) and a heterojunction bipolar transistor (HBT) is presented. By suitably modulating the width/length parameters of the MOS devices, the fabrication of this MOS-HBT-NDR circuit and its application to inverter design based on the standard 0.35 mum SiGe process was demonstrated     

Low-voltage MOBILE logic module based on Si/SiGe interbandtunnelling diodes

Si/SiGe interband tunnelling diodes have been grown by MBE on high resistivity (n^-) silicon substrates. The device enables a very low voltage, high-speed logic on a silicon substrate. A novel self-aligned diode is processed using optical lithography and dopant-selective wet chemical etching. A maximum speed index for a 60 μm² anode area device is evaluated to 2.2 ns/V resulting in a switching speed of 0.5 ns. A logic latch built of two series connected diodes (MOBILE principle) is demonstrated, showing very robust logic operation at a supply voltage as low as 0.3 V. The used technology may be employed for a co-integration with both SiGe heterostructure bipolar- and field-effect transistor technology and may contribute to future low-voltage high speed logic on Si substrates     

Mobility simulation of a novel Si/SiGe FET structure

The theoretical study of a novel Si/SiGe structure combining the advantages of buried channel MOS devices and conventional SiGe FET's is presented. A self-consistent one-dimensional Schrodinger-Poisson simulator has been developed to evaluate the gate dependence of electron effective mobility in the zero-field limit. Room temperature peak mobility values greater than 2800 cm²/Vs are predicted. The proposed structure shows also good turn-on characteristic and linear transconductance behavior, which represents a significant feature in view of possible technology applications     

SiGe-channel heterojunction p-MOSFET's

The advances in the growth of pseudomorphic silicon-germanium epitaxial layers combined with the strong need for high-speed complementary circuits have led to increased interest in silicon-based heterojunction field-effect transistors. Metal-oxide-semiconductor field-effect transistors (MOSFET's) with SiGe channels are guided by different design rules than state-of-the-art silicon MOSFET's. The selection of the transistor gate material, the optimization of the silicon-germanium channel profile, the method of threshold voltage adjustment, and the silicon-cap and gate-oxide thickness sensitivities are the critical design parameters for the p-channel SiGe MOSFET. Two-dimensional numerical modeling demonstrates that n⁺ polysilicon-gate SiGe p-MOSFET's have acceptable short-channel behavior at 0.20 μm channel lengths and are preferable to p⁺ polysilicon-gate p-MOSFET's for 2.5 V operation. Experimental results of n⁺-gate modulation-doped SiGe p-MOSFET's illustrate the importance of the optimization of the SiGe-channel profile. When a graded SiGe channel is used, hole mobilities as high as 220 cm² /V.s at 300 K and 980 cm²/V.s at 82 K are obtained     

Gas source molecular beam epitaxy grown strained-Si films on step-graded relaxed Si1−xGex for MOS applications

Gas source molecular beam epitaxy has been employed for the growth of a high quality strained-Si layer on a completely relaxed step-graded Si_1−xGe_x buffer layer. As-grown strained-Si layers have been characterized using secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, and spectroscopic ellipsometry for the determination of composition, thickness, crystalline quality, and surface roughness. Heterojunction conduction and valence band offsets (ΔE_c, ΔE_υ) of strained-Si/SiGe heterostructure have been determined from measured threshold voltages of a strained-Si channel p-metal oxide semiconductor field effect transistor (MOSFET) fabricated using grown films. MOS capacitance-voltage profiling has been employed for the extraction of strained-Si layer thickness and apparent doping profile in the device.     

An In0.52Al0.48As/n+-In0.53Ga0.47As MISFET with a modulation-doped channel

A heterostructure metal-insulator-semiconductor field-effect transistor (MISFET) with a modulation-doped channel is proposed. In this device, a very thin undoped subchannel is located between the undoped wide-bandgap insulator and a thin heavily doped channel. In the depletion mode of operation, electron transport takes place along the heavily doped channel. When the device enters the accumulation mode of operation, electrons pile up against the heterointerface in the high-mobility undoped subchannel. This results in markedly improved transport characteristics at the onset of accumulation. The concept is demonstrated in the In_0.52Al_0.48As/In_0.53 Ga_0.47As system on InP. A 1.5-μm-gate-length MISFET shows a unity current-gain cutoff frequency of 37 GHz     

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

N-Channel MOSFETs with WSi2gate

Tungsten silicide gate depletion- and enhancement-mode NMOS transistors were fabricated. The transistor characteristics revealed the excellent compatability of WSi2as gate electrode for MOS integrated circuits. Electron mobility of channel at saturation were found to be 210 cm²/v sec for enhancement-mode transistor and 110 cm²/v sec for depletion-mode transistor.     

LASOS—laser annealed silicon on sapphire

Laser annealing techniques were successfully incorporated into standard MOS/SOS processing to increase transistor channel mobility and processing yield. Silicon islands were photolithographically defined and chemically etched (by KOH) on standard SOS wafers. The islands were exposed to radiation from an excimer laser (λ = 2490 Å) having a pulse duration of 25 ns, a beam size in the range of 0.1-0.2 cm², and an energy density in the range of 0.5 - 1.0 J/cm². Using standard processing techniques MOS transistors were fabricated and characterized. It was found that exposure at an energy density of ∼0.80 J/cm²results in rounding the Si island edges, thus eliminating the "V"-shaped groove profile of the gate oxide and improving Al step coverage. The electrical characteristics of MOS transistors fabricated over laser annealed islands exhibited a 30-percent increase in channel mobility with a small negative shift (<0.2 V) in the transistor threshold voltage.     

Self-aligned GaAs p-channel enhancement mode MOS heterostructurefield-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga₂O₃ gate oxide, an undoped Al_0.75Ga_0.25As spacer layer, and undoped In_0.2Ga_0.8As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g_m of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality     

Theoretical small-signal performance of Si/SiGe/Si HBT

Application of the Monte Carlo technique to analyze electron and hole transport in bulk Si_0.8Ge_0.2 and strained Si _0.8Ge_0.2/Si is discussed. The computed minority- and majority-carrier transport properties were used in a comprehensive small-signal model to evaluate the high-frequency performance of a state-of-the-art n-p-n heterostructure bipolar transistors (HBT) fabricated with SiGe as the base material. The valence band discontinuity of a SiGe-base HBT reverses the degradation in emitter injection efficiency caused by bandgap narrowing in the base, and permits a higher ratio of base doping to emitter doping than would be practical for a bipolar transistor. Any degradative effect of increased base doping on electron and hole mobilities is offset by improved transport in the strained SiGe base, resulting in a marked decrease in the base resistance and base transit time. Compared to the Si BJT, the use of Si_0.8Ge_0.2 for the base region of an HBT leads to significant improvements in low-frequency common emitter current gain, low-frequency unilateral power gain, and maximum oscillation frequency     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress     

Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.     

Modification of most I-V characteristics by self-heating

A MOS transistor, when passing drain current, dissipates power in the channel region. This results in a temperature rise within the channel area, which can modify the I-V behaviour of the transistor. In this paper, we have calculated the channel temperature as a result of power dissipated by the device, by solving the heat diffusion equation. The modified I-V behaviour of the MOS transistor due to this channel heating has been predicted and matches experimentally observed phenomena. In particular, the negative dynamic resistance observed in the saturation region of MOS transistors operating at elevated power densities has been explained.     

Selectively doped n+ InP/n? GaInAs heterostructure prepared using chloride transport vapour-phase epitaxy

A field-effect transistor with a 2 ?m Au gate was fabricated on a selectively doped InP/GaInAs heterostructure grown using chloride transport vapour-phase epitaxy. Complete pinch-off was observed, and transconductance of 90 and 160 mS/mm were measured at 295 and 77 K, respectively. From analysis of the drain I/V characteristic, two-dimensional electron gas at the interface was revealed to be the dominant factor for the channel current. This is the first report of a successful preparation of an n+ InP/n? GaInAs heterostructure for the selectively doped field-effect transistor.