Design and implementation of an embedded 512-KB level-2 cache subsystem

Dual on-chip 512-KB unified second level (L2) caches for an UltraSparc processor are implemented using 0.13-/spl mu/m technology. Each 512-KB unit is implemented using 34 million transistors to achieve 1.4 GHz and 2.6 W at 1.3 V and 85/spl deg/C. This fully integrated subsystem is composed of conventional data and tag SRAMs along with datapaths, controller, and test engines. The unit achieves one of the shortest on-chip L2 cache latencies reported for 64-bit microprocessors, with a data latency of only four cycles including ECC correction for 128-bit data. In addition, balanced custom and automated design methodologies are used to achieve the aggressive design cycle. Architectural and physical design solutions to build this integrated short latency L2 cache are discussed.     

A 450-MHz RISC microprocessor with enhanced instruction set andcopper interconnect

This superscalar microprocessor is the first implementation of a 32-bit RISC architecture specification incorporating a single-instruction, multiple-data vector processing engine. Two instructions per cycle plus a branch can be dispatched to two of seven execution units in this microarchitecture designed for high execution performance, high memory bandwidth, and low power for desktop, embedded, and multiprocessing systems. The processor features an enhanced memory subsystem, 128-bit internal data buses for improved bandwidth, and 32-KB eight-way instruction/data caches. The integrated L2 tag and cache controller with a dedicated L2 bus interface supports L2 cache sizes of 512 KB, 1 MB, or 2 MB with two-way set associativity. At 450 MHz, and with a 2-MB L2 cache, this processor is estimated to have a floating-point and integer performance metric of 20 while dissipating only 7 W at 1.8 V. The 10.5 million transistor, 83-mm² die is fabricated in a 1.8-V, 0.20-μm CMOS process with six layers of copper interconnect     

A third-generation SPARC V9 64-b microprocessor

This quad-issue processor achieves 1-GHz operation through improved dynamic circuit techniques in critical paths and a more extensive on-chip memory system which scales in both bandwidth and latency. Critical logic paths use domino, delayed clocked domino, and logic embedded in dynamic flip-flops for minimum delay. A 64-KB sum-addressed memory data cache combines the address offset add with the cache decode, allowing the average memory latency to scale by more than the clock ratio. Memory bandwidth is improved by using wave pipelined SRAM designs for on-chip caches and a write cache for store traffic. Memory power is controlled without increased latency by use of delayed-reset logic decoders. The chip operates at 1000 MHz and dissipates less than 80 W from a 1.6-V supply. It contains 23 million transistors (12 million in RAM cells) on a 244 mm² die     

A low power scheduling scheme with resources operating at multiplevoltages

This paper presents resource and latency constrained scheduling algorithms to minimize power/energy consumption when the resources operate at multiple voltages (5 V, 3.3 V, 2.4 V, and 1.5 V). The proposed algorithms are based on efficient distribution of slack among the nodes in the data-flow graph. The distribution procedure tries to implement the minimum energy relation derived using the Lagrange multiplier method in an iterative fashion. Two algorithms are proposed, 1) a low complexity O(n²) algorithm and 2) a high complexity O(n² log(L)) algorithm, where n is the number of nodes and L is the latency. Experiments with some HLS benchmark examples show that the proposed algorithms achieve significant power/energy reduction. For instance, when the latency constraint is 1.5 times the critical path delay, the average reduction is 39%     

A Low-Power Embedded SRAM for Wireless Applications

This paper introduces a novel ultra-low-power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off between area, delay and active and passive energy consumption for low-power embedded SRAMs. The design targets wireless applications that require a moderate performance at an ultra-low-power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low-swing write technique and a distributed decoder. An 8-KB 5T SRAM was fabricated in a 0.18-mum technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32-KB SRAM.     

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-μm Technology

A passive UHF RF identification (RFID) tag IC with embedded 2-KB ferroelectric RAM (FeRAM) for rewritable applications enables a 2.9 times faster read-and-write transaction time over EEPROM-based tag ICs. The resulting FeRAM-based tag has a nominally identical communication range for both read and write operations, which is indispensable for data write applications. The evaluated tag communication range with a folded dipole antenna is from 0 m to 4.3 m, at the 953-MHz carrier frequency with 4-W transmitting Effective Isotropic Radiated Power (EIRP) from a reader/writer. The developed tag IC features two circuit blocks to maximize the communication range in 0.35-mum CMOS/FeRAM technology. First is a CMOS-only full-wave rectifier, which can improve the measured efficiency by up to 36.6% by reducing the input parasitic capacitances and optimization of multiplier structure. This efficiency is more than twice that of previously-published results. Second is a low-voltage current-mode ASK demodulator to accommodate a low-breakdown voltage of FeRAM, which converts the ASK power modulation into a linearly modulated current over an incoming power range of 27 dB, corresponding to the entire communication range. The developed demodulator can thus resolve the primary design tradeoff issue between device protection and detection sensitivity in the conventional voltage-mode demodulator     

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

This paper reports a 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using a novel two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) and sense wordline/bitline (SWL/SBL) tag-sense amplifiers with an eight-transistor (8-T) tag cell in Level 2 (L2) and a 10-T shrunk logic swing (SLS) memory cell. with the ground/floating (G/F) data sense amplifier in Level 1 (L1) for high-speed operation for low-voltage low-power VLSI system applications. Owing to the reduced loading at the SWL in the new 11-T tag cell using the WLOTC scheme, the 10-T SLS memory cell with G/F sense amplifier in L1, and the split comparison of the index signal in the 8-T tag cells with SWL/SBL tag sense amplifiers in L2, this 0.8-V cache memory implemented in a 1.8-V 0.18-/spl mu/m CMOS technology has a measured L1/L2 hit time of 11.6/20.5 ns at the average dissipation of 0.77 mW at 50 MHz.     

A 300-MHz 115-W 32-b bipolar ECL microprocessor

A full-custom single-chip bipolar ECL RISC microprocessor was implemented in a 1.0-μm single-poly bipolar technology. This research prototype contains a CPU and on-chip 2-KB instruction and 2-KB data caches. Worst-case power dissipation with a nominal -5.2 V supply is 115 W. The chip has been designed for a worst-case clock frequency of 275 MHz at a nominal supply. The chip verifies a new style of CAD tools developed during the design process, advanced packaging techniques for high-power microprocessors, and VLSI ECL circuit techniques     

A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell

This paper reports a 1-V 128-kb four-way set-associative CMOS cache memory implemented by a 0.18-μm CMOS technology using wordline-oriented tag-compare (WLOTC) structure with the 10-transistor tag cell usually for content-addressable memory (CAM) for low-voltage low-power VLSI system application. Owing to the WLOTC structure with the CAM 10-transistor tag cell for accommodating the one-step hit/miss generation and the dynamic pulse generators for realizing read-enable signals, a small hit access time (3.5 ns), low power consumption (4.1 mW at 50 MHz), and good expansion capability without sacrificing speed have been obtained     

一种低功耗有源射频识别系统的设计

研究了一种低功耗有源射频识别系统组网与设计技术,该系统可在软硬件两方面实现低功耗设计。在硬件方面,采用NORDIC公司的nRF24LE1芯片作为有源标签,nRF24L01+芯片作为节点射频芯片,STM32单片机作为节点控制芯片,实现了芯片与节点的注册与通信;软件方面,采用时分复用方法,合理分配有源芯片的时隙,设计了防冲突机制,使得芯片在极端的时间内工作,实现了低功耗组网通信。     

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit     

A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit

A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply.     

A passive UHF RFID tag chip with a dual-resolution temperature sensor in a 0.18μm standard CMOS process

This paper presents a passive EPC Gen-2 UHF RFID tag chip with a dual-resolution temperature sensor. The chip tag integrates a temperature sensor,an RF/analog front-end circuit,an NVM memory and a digital baseband in a standard CMOS process.The sensor with a low power sigma-delta(ΣΔ) ADC is designed to operate in low and high resolution modes.It can not only achieve the target accuracy but also reduce the power consumption and the sensing time.A CMOS-only RF rectifier and a single-poly non-volatile memory(NVM) are designed to realize a low cost tag chip.The 192-bit-N VM tag chip with an area of 1 mm~2 is implemented in a 0.18-μm standard CMOS process.The sensitivity of the tag is -10.7 dBm/-8.4 dBm when the sensor is disabled/enabled.It achieves a maximum reading/sensing distance of 4 m/3.1 m at 2 W EIRP.The inaccuracy of the sensor is -0.6℃/0.5℃(-1.0℃/1.2℃) in the operating range from 5 to 15℃in high resolution mode(-30 to 50℃in low resolution mode).The resolution of the sensor achieves 0.02℃(0.18℃) in high(low) resolution mode.     

A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-μm L_eff CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm×17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2× the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation     

An ultra low-voltage low power PSK backscatter modulator for passive UHF RFID tags compatible with C1 G2 EPC standard protocol

Reducing the power consumption of a passive radio frequency identification (RFID) tag is the key in many applications. As the modulator is usually the most power-hungry block in an RFID tag, this paper proposes a power-saving modulator. The proposed modulator uses phase shift keying (PSK) backscatter modulation which allows tag to communicate data from its memory to a reader by PSK modulation. The proposed modulator uses a MOSCAP as a variable impedance and is designed in a new one-inverter structure in compare to the conventional varactor-based modulators designed in two-inverter structure, as this modulator needs just a low voltage swing to drive its MOSCAP. Using MOSCAP as the variable capacitance leads to a low voltage design. Also, the fundamental equations required for determination of the capacitive impedance seen by the antenna is presented. This impedance is the master key in modulator design. The modulator has been designed, simulated and optimized in 0.18 μm CMOS technology. All possible simulation results are presented to approve its compatible operation with C1 G2 EPC global standard. The power consumption of less than 46 nW is achieved in all process corner cases at 0.8 V power supply.     

Full passive UHF RFID Tag with an ultra-low power,small area,high resolution temperature sensor suitable for environment monitoring

An UHF RFID Tag with an ultra-low power, small area, high resolution temperature sensor which adopted double voltage-controlled oscillators (VCO) has been designed and implemented using the SMIC CMOS 0.18 μm EEPROM 2P4M process. The core area of the tag (excluding the test bounding pad) is only 756×967 μm². The power-optimized tag allows a communication range of more than 6 m from a 1 W effective radiated output power reader.     

Ultra-Low Power Truly Random Number Generator for RFID Tag

This paper proposes low power, low voltage Truly Random Number Generators (TRNG) for Electrical Product Code (EPC Generation 2 Radio Frequency Identification (RFID) tag. Design considerations and trade-offs among randomicity, chip area and power consumption are analyzed according to the special requirements of Gen2 RFID tag. The proposed TRNG circuits consist of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers for post digital processing. These TRNG are implemented in SMIC 0.18 μm CMOS process. And their randomicity performances are verified by the FIPS 140-2 standard for security. One of the TRNG circuits outputs a random bit series at a speed of 40 kHz. Its power consumption is 1.04 μW and chip area is 0.05 mm². The other one has a bit rate at 48 kHz. It has a power consumption of 2.6 μW and chip area of 0.018 mm². The features of low power and small chip area in these TRNG circuits provide a good choice to solve the security and privacy problems in RFID systems.     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.     

An Ultra-Low-Power Long Range Battery/Passive RFID Tag for UHF and Microwave Bands With a Current Consumption of 700 nA at 1.5 V

We present for the first time, a fully integrated battery powered RFID integrated circuit (IC) for operation at ultrahigh frequency (UHF) and microwave bands. The battery powered RFID IC can also work as a passive RFID tag without a battery or when the battery has died (i.e., voltage has dropped below 1.3 V); this novel dual passive and battery operation allays one of the major drawbacks of currently available active tags, namely that the tag cannot be used once the battery has died. When powered by a battery, the current consumption is 700 nA at 1.5 V (400 nA if internal signals are not brought out on test pads). This ultra-low-power consumption permits the use of a very small capacity battery of 100 mA-hr for lifetimes exceeding ten years; as a result a battery tag that is very close to a passive tag both in form factor and cost is made possible. The chip is built on a 1-mum digital CMOS process with dual poly layers, EEPROM and Schottky diodes. The RF threshold power at 2.45 GHz is -19 dBm which is the lowest ever reported threshold power for RFID tags and has a range exceeding 3.5 m under FCC unlicensed operation at the 2.4-GHz microwave band. The low threshold is achieved with architectural choices and low-power circuit design techniques. At 915 MHz, based on the experimentally measured tag impedance (92-j837) and the threshold spec of the tag (200 mV), the theoretical minimum range is 24 m. The tag initially is in a "low-power" mode to conserve power and when issued the appropriate command, it operates in "full-power" mode. The chip has on-chip voltage regulators, clock and data recovery circuits, EEPROM and a digital state machine that implements the ISO 18000-4 B protocol in the "full-power" mode. We provide detailed explanation of the clock recovery circuits and the implementation of the binary sort algorithm, which includes a pseudorandom number generator. Other than the antenna board and a battery, no external components are used.