Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.     

Improvements of ozone surface treatment on the electrical characteristics and reliability in HfO2 gate stacks

In this study, we improved the interfacial properties of high-κ gate stacks with the surface treatment of ozonated water prior to deposition of hafnium oxide (HfO₂). We demonstrated that the Ozone-oxide improved the electrical properties of the HfO₂ gate stack interface in terms of its smoother interface, lower leakage current density, narrower hysteresis width, superior charge trapping effect, and reliability. From these experimental results, we believe that treatment with ozone is an efficient method for the preparation of high-quality interfaces between HfO₂ and silicon surfaces.     

Charge trapping and degradation of HfO/sub 2//SiO/sub 2/ MOS gate stacks observed with enhanced CAFM

In this letter, a prototype of conductive atomic force microscope with enhanced electrical performance has been used to separately investigate the effect of the electrical stress on the SiO/sub 2/ and the HfO/sub 2/ layers of a high-/spl kappa/ gate stack. Charge trapping in HfO/sub 2/ native defects and degradation of both layers have been observed, depending on the stress level.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

外延CeO2高k栅介质层的结构及介电性能

利用脉冲激光沉积两步生长法在Si(111)衬底上制备了厚度为10～40nm的外延CeO<,2>薄膜,构建了Pt/CeO<,2>/Si MOS结构.研究了CeO<,2>薄膜的界面及介电性能,实验发现,界面处存在的电荷对MOS结构C-V特性的测量有较大影响,采用两步生长法制备的外延CeO<,2>薄膜在保持较大介电常数的同时...     

Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-/spl kappa/ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-/spl kappa/ layer closer to the Si-SiO/sub 2/ interface enhances the 1/f noise mainly due to mobility fluctuations.     

Highly-impermeable Al2O3/HfO2 moisture barrier films grown by low-temperature plasma-enhanced atomic layer deposition

Polymer substrates are essential components of flexible electronic applications such as OTFTs, OPVs, and OLEDs. However, high water vapor permeability of polymer films can significantly reduce the lifetime of flexible electronic devices. In this study, we examined the water vapor permeation barrier properties of Al₂O₃/HfO₂ mixed oxide films on polymer substrates. Al₂O₃/HfO₂ films deposited by plasma-enhanced atomic layer deposition were transparent, chemically stable in water and densely amorphous. At 60 °C and 90% relative humidity (RH) accelerated condition, 50-nm-thick Al₂O₃/HfO₂ had water vapor transmission rate (WVTR) = 1.44 × 10⁻⁴ g m⁻² d⁻¹, whereas single layers of Al₂O₃ had WVTR = 3.26 × 10⁻⁴ g m⁻² d⁻¹ and of HfO₂ had WVTR = 6.75 × 10⁻² g m⁻² d⁻¹. At 25 °C and 40% RH, 50-nm-thick Al₂O₃/HfO₂ film had WVTR = 2.63 × 10⁻⁶ g m⁻² d⁻¹, which is comparable to WVTR of conventional glass encapsulation.     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Nanocrystalline Ge synthesis by the chemical reduction of hydrothermally grown Si0.6Ge0.4O2

Previously, we have reported the use of high pressure oxidation techniques for the growth of compositionally congruent oxides from Si_1−xGe_x. We have now used this technique as part of a two-step process of oxidation at 25 MPa and 475°C followed by reduction in 0.1 MPa (1 atm) H₂ at 700-850δC for the synthesis of nanocrystalline Ge precipitates. Using transmission electron microscopy, we show that the proposed method produces a dispersion of fine (<10 nm) precipitates of Ge embedded in an SiO₂ matrix. The structure of the oxide prior to reduction with H₂ was investigated with Fourier transform infrared spectroscopy which reveals SiO₂, GeO₂, SiO, Si-O-H, and Ge-O-H bonding states in the glass. In this paper, we discuss the thermodynamics and kinetics of both the hydrothermal oxidation technique and the proposed Ge nanocrystalline synthesis process.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation

This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step C/sub S(D)G//C/sub GS/ versus V/sub G/ curve could be identified for the device with the 1.5-nm HfO/sub 2/ gate dielectric due to the vertical and fringing displacement effects.     

Comparison of various methods for transferring graphene and few layer graphene grown by chemical vapor deposition to an insulating SiO2/Si substrate

The objective of this study is to compare the results of transferring graphene and few layer graphene (FKG) up to 5 nm thick, grown by chemical vapor deposition (CVD) at a reduced pressure to a SiO₂/Si substrate using four different polymer films. The chosen transfer methods are based on the most promising (according to published data) materials: polymethyl methacrylate, polydimethylsiloxane, thermoscotch, and polycarbonate. It is shown that the most promising transfer method (minimum resistance and maximum carrier mobility) lies in the use of polycarbonate thin films with their dissolution in chloroform. In this case, the following parameters are steadily obtained: the graphene and FLG resistance is 250–900 Ω/□ and the carrier mobility is 900–2500 cm²/(V s).     

Thermal stability of high-k Er-silicate gate dielectric formed by interfacial reaction between Er and SiO2 films

We fabricated a high-k Er-silicate gate dielectric using interfacial reaction between Er and SiO₂ films and investigated its thermal stability. The reduced capacitance with increasing annealing temperature is associated with the chemical bonding change of Er-silicate from Er-rich to Si-rich, induced by a reaction between Er-silicate and Si during thermal treatment. Further an increase in the annealing temperature (>500 °C) causes the formation of Si dangling bonds, which is responsible for an increased interface trap density.     

Aggressively scaled ultra thin undoped HfO/sub 2/ gate dielectric (EOT<0.7 nm) with TaN gate electrode using engineered interface layer

The ultrathin HfO/sub 2/ gate dielectric (EOT<0.7 nm) has been achieved by using a novel "oxygen-scavenging effect" technique without incorporation of nitrogen or other "dopants" such as Al, Ti, or La. Interfacial oxidation growth was suppressed by Hf scavenging layer on HfO/sub 2/ gate dielectric with appropriate annealing, leading to thinner EOT. As the scavenging layer thickness increases, EOT becomes thinner. This scavenging technique produced a EOT of 7.1 /spl Aring/, the thinnest EOT value reported to date for "undoped" HfO/sub 2/ with acceptable leakage current, while EOT of 12.5 /spl Aring/ was obtained for the control HfO/sub 2/ film with the same physical thickness after 450/spl deg/C anneal for 30 min at forming gas ambient. This reduced EOT is attributed to "scavenging effect" that Hf metal layer consumes oxygen during anneal and suppresses interfacial reaction effectively, making thinner interface layer. Using this fabrication approach, EOT of /spl sim/ 0.9 nm after conventional self-aligned MOSFETs process was successfully obtained.     

Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

Stacked gate dielectrics are modeled with respect to the impact on the leakage current of interfacial layers and transition regions, considering the tradeoff with the gate capacitance. A Franz 2-band dispersion model is used. Low-EOT and low-gate-current regimes are explored theoretically using reasonable estimates guided by experimental data. Transition layer values of each parameter are qualitatively explored for oxynitride, Si/sub 3/N/sub 4//SiO/sub 2/, and high-K stacks. Higher dielectric constant and more insulating materials are obviously desired for each layer of dielectric; however, the transition region becomes more important as such dielectrics are considered. Higher dielectric constant of interfacial layer is desirable for the low-EOT-low-gate-current requirement.     

Top-TiN生长条件及TaN厚度对MOSCAP栅叠层有效功函数的影响

我们引入TaN/TiAl/top-TiN三层结构,通过变化TaN的厚度及top-TiN的生长条件来调节TiN-based金属栅叠层的有效功函数。实验结果显示：较薄的TaN和PVD-process生长的top-TiN组合可以得到较小的有效功函数(EWF),而较厚的TaN和ALD-process生长的top-TiN组合可以得到较大的有效功函数(EWF),文中EWF有从4.25eV to 4.56eV的变化。同时文中也给出了TaN厚度及top-TiN的生长条件调节有效功函数(EWF)的物理解释。与PVD-process在室温条件下生长TiN相比,ALD-process TiN是在400 ℃条件下生长的,400 ℃ ALD-process TiN 可以为整个工艺过程提供更多的热预算,从而促进更多的Al原子扩散进入top-TiN,导致扩散进入到bottom-TiN的Al原子数量减少。另外,厚的TaN也会阻止Al原子进入bottom-TiN。这些因素都减少了bottom-TiN中Al原子的数量,减弱了Al原子对有效功函数的调节作用,从而引起EWF的增加。     

Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO/sub 2/ gate dielectrics

Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitride and HfO/sub 2/ gate dielectrics on [110] surfaces compared with [100]. CMOS drive current is nearly symmetric on [110] orientation without any degradation of subthreshold slope. For HfO/sub 2/ gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on [110] substrates at L/sub poly/=0.12 /spl mu/m, while current reduction in nMOS is around 26%.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Low-frequency noise in TaSiN/HfO/sub 2/ nMOSFETs and the effect of stress-relieved preoxide interfacial layer

Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO/sub 2/ on thermal SiO/sub 2/ with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO/sub 2/ resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO/sub 2/ dielectric. Consequently, a lower oxide trap density of /spl sim/4/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ is extracted compared to over 3/spl times/10/sup 18/ cm/sup -3/eV/sup -1/ values reported for poly Si devices indicating an improvement in the high-/spl kappa/ and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO/sub 2/ MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm/sup 2//V/spl middot/s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO/sub 2/ are found to exhibit at least /spl sim/10% higher effective mobility than RCA devices, notwithstanding the differences in the high-/spl kappa/ and interfacial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO/sub 2/, which, in part, contributes to the mobility improvement.