High mobility,low voltage polymer transistor

We introduce a polymer transistor that operates with low supply voltage and yet has a field-effect mobility higher than the mobilities reported for low voltage polymer transistors. A simple plasma oxidation of the gate metal to form a thin (3.74 nm) top metal oxide layer in the gate metal is involved in the fabrication that acts as the gate dielectric. With ultrathin gate dielectrics, the variation in the dielectric thickness and the surface roughness scattering can severely limit the mobility attainable. The plasma oxidation under certain conditions produces a very smooth oxide surface, leading to the high mobility.     

Channel Protection Layer Effect on the Performance of Oxide TFTs

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al‐doped zinc tin oxide (AZTO) TFT. Deposition of an ultra‐thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo‐resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.     

The impact of self-assembled monolayer thickness in hybrid gate dielectrics for organic thin-film transistors

We have investigated the electrical characteristics of hybrid dielectrics with a thickness of 6 nm or less that are composed of a plasma-grown aluminum oxide (AlO_x) layer and a self-assembled monolayer (SAM) of an aliphatic phosphonic acid. The impact of the quality of the AlO_x layer on the insulating properties of the double-layer dielectrics was assessed by comparing two different oxidation procedures, and the influence of the thickness of the organic SAM was evaluated by employing molecules with five different chain lengths. In order to decouple the relative contributions of the oxide and the SAM to the performance of the double-layer dielectrics we have also performed cyclic voltammetry measurements on indium tin oxide (ITO)/SAM devices without AlO_x layer. Finally, we have evaluated how the quality of the AlO_x layer and the thickness of the SAM affect the performance of low-voltage organic thin-film transistors (TFTs) that employ the thin AlO_x/SAM dielectrics as the gate dielectric. The results confirm the important role of the SAM in determining the breakdown voltage, in limiting the current density, and in compensating the somewhat lower quality of AlO_x layers produced under mild plasma conditions.     

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al₂O₃ gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface     

1 Volt organic transistors with mixed self-assembled monolayer/Al2O3 gate dielectrics

Control of the threshold voltage and the subthreshold swing is critical for low voltage transistor operation. In this contribution, organic field-effect transistors (OFETs) operating at 1 V using ultra-thin (∼4 nm), self-assembled monolayer (SAM) modified aluminium oxide layers as the gate dielectric are demonstrated. A solution-processed donor–acceptor semiconducting polymer poly(3,6-di(2-thien-5-yl)-2,5-di(2-octyldodecyl)-pyrrolo[3,4-c]pyrrole-1,4-dione)thieno[3,2-b]thiophene) (PDPP2TTT) is used as the active layer. It is shown that the threshold voltage of the fabricated transistors can be simply tuned by carefully controlling the composition of the applied SAM. The optimised OFETs display threshold voltages around 0 V, low subthreshold slopes (150 ± 5 mV/dec), operate with negligible hysteresis and show average saturated field-effect mobilities in excess of 0.1 cm²/V s at 1 V.     

Hybrid Nanodielectrics for Low‐Voltage Organic Electronics

Nanoscale hybrid dielectrics composed of an ultra‐thin polymeric low‐κ bottom layer and an ultra‐thin high‐κ oxide top layer, with high dielectric strength and capacitances up to 0.25 μFcm^?2, compatible with low‐voltage, low‐power, organic electronic circuits are demonstrated. An efficient and reliable fabrication process, with 100% yield achieved on lab‐scale arrays, is demonstrated by means of pulsed laser deposition (PLD) for the fast growth of the oxide layer. With this strategy, high capacitance top gate (TG), n‐type and p‐type organic field effect transistors (OFETs) with high mobility, low leakage currents, and low subthreshold slopes are realized and employed in complementary‐like inverters, exhibiting ideal switching for supply voltages as low as 2 V. Importantly, the hybrid double‐layer allows for a neat decoupling between the need for a high capacitance, guaranteed by the nanoscale thickness of the double layer, and for an optimized semiconductor–dielectric interface, a crucial point in enabling high mobility OFETs, thanks to the low‐κ polymeric dielectric layer in direct contact with the polymer semiconductor. It is shown that such decoupling can be achieved already with a polymer dielectric as thin as 10 nm when the top oxide is deposited by PLD. This paves the way for a very versatile implementation of the proposed approach for the scaling of the operating voltages of TG OFETs with very low level of dielectric leakage currents to the fabrication of low‐voltage organic electronics with drastically reduced power consumption.     

Prospects of manufacturing organic semiconductor-based integratedcircuits

The driving force for developing organic thin-film transistor (OTFT)-based electronics is the fact that they are flexible, lightweight and have the prospect of low-cost manufacturing. Major barriers in the practical realization of OTFT-based electronic systems are the need for larger power supplies, lower gain, lower switching speeds and reliability problems. New directions leading to changes in the design of transistors, materials used in the fabrication, and processing techniques are warranted for developing process and equipment that can lead to the manufacturing of OTFT-based electronics. For developing dense OTFT-based electronics, the low thermal conductivity (as compared to silicon) of organic semiconductors is a fundamental problem. The use of nanodimension polymers with homogeneous microstructure, transistors operating in subthreshold region and the use of new materials (high and low dielectric constant dielectric materials as well as Cu as the conductor for interconnections) for fabricating transistors and a novel rapid photothermal processing technique for depositing thin films of organic semiconductors as well as for reducing the defects introduced during processing are some of the proposed directions that may lead to the manufacturing of OTFT based electronics     

Integration of silk protein in organic and light-emitting transistors

We present the integration of a natural protein into electronic and optoelectronic devices by using silk fibroin as a thin film dielectric in an organic thin film field-effect transistor (OFET) ad an organic light emitting transistor device (OLET) structures. Both n- (perylene) and p-type (thiophene) silk-based OFETs are demonstrated. The measured electrical characteristics are in agreement with high-efficiency standard organic transistors, namely charge mobility of the order of 10(-2) cm(2)/Vs and on/off ratio of 10(4). The silk-based optolectronic element is an advanced unipolar n-type OLET that yields a light emission of 100nW.     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device     

Fabrication of microcrystalline silicon TFTs using a high-densityplasma approach

N-channel microcrystalline silicon (mc-Si) thin film transistors (TFTs) were fabricated using a high density plasma (HDP) approach. An electron cyclotron resonance (ECR) plasma source was employed to deposit all of the thin film materials needed for the transistor; that is, intrinsic mc-Si, n-type mc-Si, and dielectric silicon dioxide were grown with the ECR high density plasmas and the deposition rates for these films were in the range of 120-150 Å/min. The substrate temperatures during these depositions were maintained below 285°C. To complete the fabrication of these TFTs, we used only two masks with one alignment. After 1 h annealing under forming gas atmosphere, the mc-Si TFTs perform with linear field effect mobility of 12 cm²/V-s, on/off ratio of 10⁶, subthreshold swing of 0.3 V/decade, off-current of 4×10^-13 A/μm and threshold voltage of 5 V     

具有双绝缘层的有机薄膜晶体管

为了提高SiO2单绝缘层器件的性能,在SiO2绝缘层的表面用旋涂的方法制备一层大约50 nm厚度的PMMA.实验结果表明用无机/有机双绝缘层可以有效的提高器件的性能同时降低器件的漏电流.计算出了载流子迁移率和开关电流比,基于PMMA/SiO2双绝缘层器件的载流子迁移率和开关电流比分别是4.0×10-3cm2/Vs和104.     

Parasitic MOSFET degradation induced by Fowler-Nordheim injection

Degradation induced by Fowler-Nordheim (F-N) electron injection is observed in a parasitic MOS transistor associated with a MOS transistor's edge region. A bump appears in the subthreshold region of both an n-channel transistor after positive gate biased F-N injection and a p-channel transistor after negative gate biased F-N injection. It is found that the effective gate-oxide thickness of a parasitic transistor is 30 nm. As thinner gate oxide is used, the amount of the charge injected into the gate oxide may increase due to increased electric fields     

Simultaneous Modification of Bottom‐Contact Electrode and Dielectric Surfaces for Organic Thin‐Film Transistors Through Single‐Component Spin‐Cast Monolayers

An efficient process is developed by spin‐coating a single‐component, self‐assembled monolayer (SAM) to simultaneously modify the bottom‐contact electrode and dielectric surfaces of organic thin‐film transistors (OTFTs). This effi cient interface modifi cation is achieved using n‐alkyl phosphonic acid based SAMs to prime silver bottom‐contacts and hafnium oxide (HfO₂) dielectrics in low‐voltage OTFTs. Surface characterization using near edge X‐ray absorption fi ne structure (NEXAFS) spectroscopy, X‐ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR‐FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well‐defi ned phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n‐channel (C₆₀) and p‐channel (pentacene) based OTFTs. Specifi cally, SAMs of n‐octylphos‐phonic acid (OPA) provide both low‐contact resistance at the bottom‐contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO₂ dielectric bottom‐contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm‐cm), low subthreshold swing (as low as 75 mV dec^?1), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm² V^?1 s^?1, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom‐contact OTFTs.     

Organic Thin‐Film Transistors: Simultaneous Modification of Bottom‐Contact Electrode and Dielectric Surfaces for Organic Thin‐Film Transistors Through Single‐Component Spin‐Cast Monolayers (Adv. Funct. Mater. 8/2011)

An efficient process is developed by spin‐coating a single‐component, self‐assembled monolayer (SAM) to simultaneously modify the bottom‐contact electrode and dielectric surfaces of organic thin‐film transistors (OTFTs). This effi cient interface modifi cation is achieved using n‐alkyl phosphonic acid based SAMs to prime silver bottom‐contacts and hafnium oxide (HfO₂) dielectrics in low‐voltage OTFTs. Surface characterization using near edge X‐ray absorption fi ne structure (NEXAFS) spectroscopy, X‐ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR‐FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well‐defi ned phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n‐channel (C₆₀) and p‐channel (pentacene) based OTFTs. Specifi cally, SAMs of n‐octylphos‐phonic acid (OPA) provide both low‐contact resistance at the bottom‐contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO₂ dielectric bottom‐contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm‐cm), low subthreshold swing (as low as 75 mV dec^?1), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm² V^?1 s^?1, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom‐contact OTFTs.     

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain–frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.     

Solution-Processed High-<Emphasis Type="Italic">k</Emphasis> Dielectric,ZrO<Subscript>2</Subscript>, and Integration in Thin-Film Transistors

We report a sol–gel method to deposit a high-k dielectric, zirconium oxide (ZrO₂). This solution-based approach has advantages of easy processing and low fabrication cost. Effects of annealing temperatures on dielectric properties, such as tunneling current density and capacitance density, are reported. Morphological and chemical characterizations suggest that the process temperature can be kept at or below 300°C. We have employed the solution-processed ZrO₂ dielectric in a zinc tin oxide thin-film transistor. Saturation mobility of 4.0 cm²/V s at operating voltage of 2 V has been observed. The measured subthreshold swing is 74 mV/decade, which is the result of the combination of an electronically clean dielectric/semiconductor interface and high insulator capacitance.     

Synthesis and Characterization of Naphthalene End-Capped Divinylbenzene for OTFT

An organic field-effect transistor was fabricated based on a thin film of 1,4-bis-(2-naphthalen-2-ylvinyl)benzene (BNDV). The organic semiconductor was deposited via thermal evaporation on a chemically modified silicon dioxide surface. The thermal, optical, electronic, and surface properties of the BNDV compound were investigated by thermogravimetric analysis, differential scanning calorimetry, ultraviolet–visible (UV–vis) absorption, photoluminescence spectroscopies, cyclic voltammetry, x-ray diffraction, and atomic force microscopy. The BNDV had good oxidation stability and exhibited a field-effect performance with a mobility of 0.062 cm²/V s, a subthreshold slope of 0.4 V, and an on/off ratio of 2.45 × 10⁵.     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.     

ZnO as a dielectric for organic thin film transistor-based non-volatile memory

This paper demonstrates the novel application of d.c. sputtered zinc oxide (ZnO) as a charge trapping dielectric material for the application of an organic thin film transistor (OTFT) based non-volatile memory (NVM). The motivation of using ZnO as a dielectric is due to its chemical stability and optical transparency, enabling future development of transparent electronic devices. Unbalanced magnetron d.c. sputtering with Ar:O₂ ratio of 80:20 was used to obtained a ZnO dielectric of 50 nm thick. The ZnO has an optical band gap of 3.23 eV, resistivity and k-value of 5 × 10⁷ Ω-cm and 50, respectively. The ZnO sandwiched between two layers of low-k methyl-silsesquioxane (MSQ) sol–gel dielectric creates a triple layer dielectric structure for charge storage. A solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene, was used as an active layer of an OTFT-NVM. It has been successfully demonstrated that this OTFT-NVM can be electrically programmed and erased at a low voltage.     

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.