Silicon in functional epitaxial oxides: A new group of nanostructures

The ability to integrate low-dimensional crystalline silicon into crystalline insulators with high dielectric constant (high-k) can open the way for a variety of novel applications ranging from high-k replacement in future nonvolatile memory devices to insulator/Si/insulator structures for nanoelectronic applications. We will present an approach for nanostructure fabrication by incorporation of crystalline silicon into epitaxial oxide that is based on a solid-phase epitaxy of Si. In dependence on the preparation conditions we obtained nanostructures containing an either ultra-thin single-crystalline Si quantum-well buried in single-crystalline oxide matrix with sharp interfaces or Si-nanocrystals (ncs) embedded into single-crystalline oxide layer. As an example, we demonstrate the growth of Si buried in Gd₂O₃ and the incorporation of epitaxial Si clusters into single-crystalline Gd₂O₃ on silicon as well as silicon carbide substrates using molecular beam epitaxy. The leakage current of the obtained nanostructures exhibited negative differential resistance at lower temperatures. For structures containing Si-ncs a large hysteresis in capacitance–voltage measurements due to charging and discharging of the Si-ncs was obtained.     

Integration of low dimensional crystalline Si into functional epitaxial oxides

In this work we show that by efficiently exploiting the growth kinetics during molecular beam epitaxy (MBE) one could create Si nanostructures of different dimensions. Examples are Si quantum dots (QD) or quantum wells (QW), which are buried into an epitaxial rare-earth oxide, e.g. Gd₂O₃. Electrical measurements carried out on Pt/Gd₂O₃/Si MOS capacitors comprised with Si-QD demonstrate that such well embedded Si-QD with average size of 5 nm and density of 2×10¹² cm⁻² exhibit very good charge storage capacity with suitable retention (∼10⁵ s) and endurance (∼10⁵ write/erase cycles) characteristics. The Pt/Gd₂O₃/Si (metal-oxide-semiconductor (MOS)) basic memory cells with embedded Si-QD display large programming window (∼1.5-2 V) and fast writing speed and hence could be a potential candidate for future non-volatile memory application. The optical absorption of such Si-QD embedded into epitaxial Gd₂O₃ was found to exhibit a spectral threshold maximum up to 2.9±0.1 eV depending on their sizes, inferring a significant influence of quantum confinement on the QD/oxide interface band diagram.Ultra-thin single-crystalline Si-QW with epitaxial insulator (Gd₂O₃) as the barrier layers were grown by a novel approach based on cooperative vapor phase MBE on Si wafer with sharp interfaces between well and barriers. The current-voltage characteristics obtained for such structure exhibits negative differential resistance at lower temperature, making them a good candidate for resonant tunneling devices.     

Epitaxial, high-K dielectrics on silicon: the example of praseodymium oxide

We show the first results for crystalline growth of praseodymium oxide on Si as a potential high-K dielectric with very promising electrical properties. All layer growth experiments were performed using solid source molecular beam epitaxy. The initial growth phase was studied using scanning tunneling microscopy. On Si(0 0 1) oriented surfaces, crystalline Pr₂O₃ grows as (1 1 0)-domains, with two orthogonal in-plane orientations. Epitaxial silicon overgrowth seems to be impossible. We obtain perfect epitaxial growth on Si(1 1 1). These layers can also be overgrown epitaxially with silicon. Finally, we show that the structural quality of epitaxial grown Pr₂O₃ on Si(0 0 1) degrades when the film is exposed to air due to silicon oxide formation at the interface based on oxygen indiffusion. However, it can be stabilized by capping with Si.     

Molecular-beam epitaxy of mercury-cadmium-telluride solid solutions on alternative substrates

Growth processes were considered for heteroepitaxial structures based on a mercury-cadmium-telluride (MCT) solid solution deposited on GaAs and Si alternative substrates by molecular-beam epitaxy. Physical and chemical processes of growth and defect-generation mechanisms were studied for CdZnTe epitaxy on atomically clean singular and vicinal surfaces of gallium-arsenide substrates and CdHgTe films on CdZnTe/GaAs surfaces. ZnTe single-crystalline films were grown on silicon substrates. Methods for reducing the content of defects in CdZnTe/GaAs and CdHgTe films were developed. Equipment for molecular-beam epitaxy was designed for growing the heteroepitaxial structures on large-diameter substrates with a highly uniform composition over the area and their control in situ. Heteroepitaxial MCT layers with excellent electrical parameters were grown on GaAs by molecular-beam epitaxy.     

Growth and structural properties of crystalline LaAlO3 on Si (0 0 1)

Crystalline LaAlO₃ was grown by oxide molecular beam epitaxy (MBE) on Si (0 0 1) surfaces utilizing a 2 ML SrTiO₃ buffer layer. This SrTiO₃ buffer layer, also grown by oxide MBE, formed an abrupt interface with the silicon. No SiO₂ layer was detectable at the oxide-silicon interface when studied by cross-sectional transmission electron microscopy. The crystalline quality of the LaAlO₃ was assessed during and after growth by reflection high energy electron diffraction, indicating epitaxial growth with the LaAlO₃ unit cell rotated 45° relative to the silicon unit cell. X-ray diffraction indicates a (0 0 1) oriented single-crystalline LaAlO₃ film with a rocking curve of 0.15° and no secondary phases. The use of SrTiO₃ buffer layers on silicon allows perovskite oxides which otherwise would be incompatible with silicon to be integrated onto a silicon platform.     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

Epitaxial spinel growth for integrated circuits

This is a report on our investigation of the epitaxial growth of Si-on-spinel-on-Si double-heterostructure integrated circuit material. The spinel epitaxial layers were grown on the Si substrate with an open-tube Al-HCl-MgCl₂-CO₂H₂ VPE system. High electron Hall-mobility and low defect density in the active Si layers were achieved with optimum growth conditions for spinel and silicon. Bipolar transistors, MOS devices and high-voltage bipolar ICs were fabricated in the active Si layers on epitaxially grown spinel.     

The In/PbTe barrier structures with a thin intermediate insulating layer

Epitaxial n-PbTe layers were grown on BaF₂ {111} single-crystal substrates by hot-wall epitaxy from the gaseous phase. These layers were kept in atmospheric air for 15–30 days, after which In and protective BaF₂ layers were deposited. Current-voltage characteristics and photoelectric sensitivity spectra of the In/n-PbTe barrier structures were measured in the temperature range T=80–300 K. Based on the experimental results, a model of charge transport is suggested and the effective barrier height ? _b ^eff , the insulator layer thickness δ, and the surface-state density D _S are determined.     

Epitaxial growth and electrical conductance of metal(CoSi2)/insulator(CaF2) nanometer-thick layered structures on Si (111)

Epitaxial growth of a metal (CoSi₂) /insulator (CaF2) nanometer-thick layered structure on Si(111) was demonstrated and the resistivity of CoSi₂ epilayer in this structure was investigated. An epitaxial CoSi₂ layer on CaF₂ was obtained by the two-step growth technique,i.e. solid phase epitaxy with the epitaxial Si layer grown in the first step and Co deposited in the second step. This technique was shown to be effective to avoid the Co agglomeration on CaF₂ layer observed in the co-evaporation of Si and Co. An epitaxial CaF₂ layer was formed on CoSi₂/CaF₂ at low substrate temperature (450°C) with partially ionized and accelerated CaF₂ beam, to avoid Co agglomeration in the CoSi₂/CaF₂ underlayer as well. Obtained results showed a single-crystalline nature in reflection high-energy electron diffraction (RHEED) and transmission electron microscopy (TEM) observations. The resistivity of a few nm-thick CoSi₂ epilayers embedded by CaF₂ has been investigated. We studied thickness and annealing temperature dependence of resistivity and showed that a minimum resistivity of 30 μΩ cm was obtained in a 2 nm-thick CoSi₂ sample annealed at 860°C.     

Epitaxial growth of LaAlO3 on Si(0 0 1) using interface engineering

In this work, the potentiality of molecular beam epitaxy techniques to prepare epitaxial lanthanum aluminate (LaAlO₃) films on Si(0 0 1) is explored. We first demonstrate that the direct growth of LaAlO₃ on Si(0 0 1) is impossible : amorphous layers are obtained at temperatures below 600 °C whereas crystalline layers can be grown at higher temperatures but interfacial reactions leading to silicate formation occur. An interface engineering strategy is then developed to avoid these reactions. SrO and SrTiO₃ have been studied as buffer for the subsequent growth of LaAlO₃. Only partial LaAlO₃ epitaxy is obtained on SrO whereas high quality layers are achieved on SrTiO₃. However both SrO and SrTiO₃ appear to be unstable with respect of Si at the growth temperature of LaAlO₃ (700 °C). This leads to the formation of relatively thick amorphous interfacial layers. Despite their instability at high temperature, these processes could be used for the fabrication of twins-free LaAlO₃ templates on Si, and for the fabrication of complex oxide/Si heterostructures for various applications.     

Enhanced electrical properties of nominally undoped Si/SiGe heterostructure nanowires grown by molecular beam epitaxy

Electrical properties of epitaxial single-crystalline Si/SiGe axial heterostructure nanowires (NWs) on Si〈1 1 1〉 substrate were measured by contacting individual NWs with a micro-manipulator inside an scanning electron microscope. The NWs were grown by incorporating compositionally graded Si_1−xGe_x segments of a few nm thicknesses in the Si NWs by molecular beam epitaxy. The I-V characteristics of the Si/SiGe heterostructure NWs showed Ohmic behavior. However, the resistivity of a typical heterostructure NW was found to be significantly low for the carrier concentration extracted from the simulated band diagram. Similarly grown pure Si and Ge NWs showed the same behavior as well, although the I-V curve of a typical Si NW was rectifying in nature instead of Ohmic. It was argued that this enhanced electrical conductivities of the NWs come from the current conduction through their surface states and the Ge or Si/SiGe NWs are more strongly influenced by the surface than the Si ones.     

Electrical and optical properties of near-surface AlGaAs/InGaAs/AlGaAs quantum wells with different quantum-well depths

A series of AlGaAs/InGaAs/AlGaAs quantum-well heterostructures with different quantum-well depths and approximately the same concentrations of two-dimensional electrons is grown by molecular-beam epitaxy. The built-in electric field in the grown samples is determined from the photoreflectance data and, on this basis, the energy-band structure in the quantum-well region is calculated. It is found that the highest mobility μ_e of two-dimensional electrons is attained in the sample with a barrier-layer thickness of L _b = 11 nm. Measurements of the photoluminescence spectra and the band-structure calculations demonstrate that, as the quantum well becomes closer to the surface, the doping profile broadens due to diffusion and segregation processes. The nonmonotonic dependence of μ_e on the distance between the surface and the quantum well is explained.     

High-Quality (211)B CdTe on (211)Si Substrates Using Metalorganic Vapor-Phase Epitaxy

High-quality (211)B CdTe buffer layers are required during Hg_1−x Cd _x Te heteroepitaxy on Si substrates. In this study, direct metalorganic vapor-phase epitaxy (MOVPE) of (211)B CdTe on Si, as well as CdTe on Si using intermediate Ge and ZnTe layers, has been achieved. Tertiary butyl arsine was used as a precursor to enable As surfactant action during CdTe MOVPE on Si. The grown CdTe/Si films display a best x-ray diffraction rocking-curve full-width at half-maximum of 64 arc-s and a best Everson etch pit density of 3 × 10⁵ cm⁻². These values are the best reported for MOVPE-grown (211)B CdTe/Si and match state-of-the-art material grown using molecular-beam epitaxy.     

Process integration of Pr-based high-k gate dielectrics

We present the process integration of the Pr-based high-k oxides Pr₂O₃, PrTi_xO_y and Pr_xSi_yO_z for CMOS devices. MOS structures were grown in form of p⁺ poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF₄/O₂ plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H₂SO₄ solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated Pr_xSi_yO_z are presented.     

Au/SnO2/n-Si (MOS) structures response to radiation and frequency

Metal-insulator-semiconductor (MOS) structures with insulator layer thickness of 290 Å were irradiated using a ⁶⁰Co (γ-ray) source and relationships of electrical properties of irradiated MOS structures to process-induced surface defects have been investigated both before and after γ-irradiation. The density of surface state distribution profiles of the sample Au/SnO₂/n-Si (MOS) structures obtained from high-low frequency capacitance technique in depletion and weak inversion both before and after irradiation. The measurement capacitance and conductance are corrected for series resistance. Series resistance (Rs) of MOS structures were found both as function of voltage, frequency and radiation dose. The C(f)-V and G(f)-V curves have been found to be strongly influenced by the presence of a dominant radiation-induced defects. Results indicate interface-trap formation at high dose rates (irradiations) is reduced due to positive charge build-up in the semiconductor/insulator interfacial region (due to the trapping of holes) that reduces the flow rate of subsequent holes and protons from the bulk of the insulator to the Si/SnO₂ interface. The series resistance decreases with increasing dose rate and frequency the radiation-induced flat-band voltage shift in 1 V. Results indicate the radiation-induced threshold voltage shift (ΔV_T) strongly dependence on radiation dose rate and frequency.     

Plasmon–phonon coupling in the infrared reflectance spectra of Bi<Subscript>2</Subscript>Se<Subscript>3</Subscript> films

The results of studies of optical reflection in the far- and mid-infrared spectral regions are reported. The reflectance of five Bi₂Se₃ topological insulator films grown by molecular-beam epitaxy on Si(111) substrates is measured. The characteristic parameters of phonons and plasmons are determined by means of dispersion analysis for multilayer structures. It is found that the plasma frequency in a layer close to the Si–film interface is noticeably higher than that in the film bulk. Calculations of the loss function show that plasmon–phonon coupling plays an important role in Bi₂Se₃ films. The attenuated total internal reflection method is used to determine the frequency of the surface plasmon–phonon mode.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy

Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd₂O₃ prepared by molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO₂ prepared by reactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.     

Growth and characterization of InAsSb layers on GaSb substrates by liquid phase epitaxy

High quality InAs_1−xSb_x semiconductor films were successfully grown on (100) GaSb single crystal substrates using liquid phase epitaxy technique (LPE). The crystalline structure and lattice mismatch between film and substrate were investigated by high-resolution X-ray diffraction (HRXRD). The surface roughness and the interface morphology of the epitaxial film-on-substrate were characterized by atomic force microscopy (AFM), scanning electron microscopy (SEM) and optical microscopy. These results show the high-purity InAs_1−xSb_x epitaxial layers with mirror-like surface and rms ranges from 0.5 to 2 nm, and a sharp interface between substrate and ternary film. The optical properties of the layers were studied by low temperature photoluminescence (PL) spectroscopy. PL spectrum of the ternary film shows one radiative emission peak with narrow full width at half-maximum, which is an evidence of the good crystalline quality of the epilayer. It is worth to mention that the InAsSb films were grown on GaSb substrates for compositions of Sb with x=0.16 without introducing any intermediate composition buffer layer between the GaSb substrate and the film as reported in previous works.     

Static current-voltage characteristics of Au/CaF<Subscript>2</Subscript>/<Emphasis Type="Italic">n</Emphasis>-Si(111) MIS tunneling structures

Using molecular-beam epitaxy, Au/CaF₂/n-Si(111) structures were fabricated that exhibit lower currents at a given fluoride film thickness (1.5–2 nm) than those of all similar structures studied. At a positive voltage at the metal, the current is in agreement with that calculated within the model with conservation of the transverse component of the wave vector during tunneling transport. Relative contributions of electron and hole components were analyzed for forward and reverse biases. The effect of the nonuniform distribution of the insulator thickness over the area on measured currents was estimated. The thin CaF₂ layers that were grown are potentially applicable as barrier layers in various devices of functional electronics.