多层空气隙Cu互连结构耦合电容的优化

随着超大规模集成电路特征尺寸不断缩小,多层cu互连之间的RC延迟成为一个越来越严重的问题.由于低介电常数(low-k)材料配合空气隙(air gap)结构可用于降低Cu互连导线间的耦合电容从而改善RC延迟特性,建立了单层和多层空气隙Cu互连结构的有限元分析模型,以研究空气隙结构尺寸与互连介质等效介电常数的关系.结果表明,在单层空气隙Cu互连结构中,通过增加互连导线间空气隙的结构尺寸可以减小Cu互连结构中的耦合电容,进而改善RC延迟特性;在多层空气隙Cu互连结构中,通过改变IMD和ILD中空气隙的尺寸结构可以得到RC延迟性能优化的多层空气隙Cu互连结构.     

Materials' impact on interconnect process technology and reliability

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

倒装焊器件尺寸参数对低k层及焊点的影响

当前。集成电路制造中低k介质与铜互连集成工艺的引入已经成为一种趋势,因此分析封装器件中低矗结构的可靠性是很有必要的。利用有限元软件分析了倒装焊器件的尺寸参数对低k层及焊点的影响。结果表明：减薄芯片,减小PI层厚度,增加焊点高度,增加焊盘高度,减小基板厚度能够缓解低k层上的最大等效应力;而减薄芯片,增加PI层厚度,增加焊点高度,减小焊盘高度,减小基板厚度能够降低焊点的等效塑性应变。     

Nanotechnology copper interconnect processes integrations for high aspect ratio without middle etching stop layer

As design rules for interconnection tend to result in the reduction of silicon chip size, devices have been miniaturized and fabrication processes have become more complex. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process integration require a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. To create highly reliable electrical interconnects, the interfaces between the Cu metal and low-k must be optimized during the lithography, etching, ashing and copper processes. For higher aspect ratios interconnect profiles, however this approach leads to increased sidewall roughness and undercut. To suppress problems in the fabrication processes, the balance of the processes integration should be quantitatively and instantaneously controlled to the optimum manufacturing technologies. These process characteristics and manufacturing mechanism optimization will also be discussed.     

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity.     

集成电路铜互连线及相关问题的研究

论述了Cu作为互连金属的优点、面临的主要问题及解决方案,介绍了制备Cu互连线的双镶嵌工艺及相关工艺问题,讨论了Cu阻挡层材料的作用及选取原则,对低k材料的研究的进展情况也了简要的介绍。     

Effect of in-line electron beam treatment on the electrical performance of Cu/organic low-k damascene interconnects

The interface quality and reliability issues have shown significant importance in Cu/organic low-k damascene integration. In this letter, a post-etch in-line electron beam (E-beam) treatment was used to modify the interface properties of sidewall barrier/organic low-k dielectric without impairing either the film properties or the dielectric constant. X-ray photoelectron spectroscopy (XPS) analysis indicated that oxygen content at the low-k surface, which mostly came from oxygen/moisture intake from ambient during process, was eliminated by E-beam exposure and subsequent rapid thermal annealing. As a result, Cu/organic low-k interconnects exhibited a lower line-to-line leakage current and a higher breakdown strength. The interconnect structures, after this in-line E-beam treatment process, also showed a good reliability performance against thermal stress, with good leakage current characteristics after a 500-h burn-in at 200/spl deg/C.     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

Patterning of narrow porous SiOCH trenches using a TiN hard mask

For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO₂ hard mask may lead to severe profile distortions, attributed to TiF_x compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.     

新型低介电常数材料研究进展

在超大规模集成电路中,随着器件集成度的提高和延迟时间的进一步减小,需要应用新型低介电常数(k<3)材料。本文介绍了当前正在研究和开发的几种低介电材料,其中包括聚合物、掺氟、多孔和纳米介电材料。     

集成电路片内铜互连技术的发展

论述了铜互连取代铝互连的主要考虑,介绍了铜及其合金的淀积、铜图形化方法、以及铜与低介电常数材料的集成等。综述了ULSI片内铜互连技术的发展现状。     

Packaging of copper/low-k IC devices: a novel direct fine pitch gold wirebond ball interconnects onto copper/low-k terminal pads

The trend toward finer pitch and higher performance devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. Compared to the commonly used aluminum metallization scheme on the traditional silicon dioxide and/or silicon nitride passivation, a Cu/low-k combination offers higher on-chip communication speed and a lower overall device cost. However, the process of packaging Cu/low-k devices has been proven to be difficult, relying either on additional lithography and deposition steps or on costly new process tools. Thus, this paper presents a novel methodology to bond fine pitch Au wire directly onto the Cu/low-k pad structure using the industry standard tool set. A Cu/low-k test vehicle is designed with the required slotted low-k fillings for dual damascene chemical mechanical polishing (CMP) process need. In addition, a thin organic passivation film is developed for coating the exposed Cu/low-k pad temporarily from copper oxidation and to provide a wirebondable surface to form the proper interconnects. A design of experiment is performed to optimize wirebonding parameters [power, time, and ultrasonic gauge (USG) bleed], along with key physical contributors from wafer sawing and die attaching steps that impact the interconnect shear strength and quality. In addition, electrical and optical characterization and surface failure analysis are performed to confirm the feasibility of the technology. Finally, reliability results of the pad structure design and recommendations for further process optimization are presented.     

超深亚微米集成电路中的互连问题--低k介质与Cu的互连集成技术

半导体集成电路技术的发展对互连技术提出了新的需求,互连集成技术在近期和远期发展中将面临一系列技术和物理限制的挑战,其中Cu互连技术的发明是半导体集成电路技术领域中具有革命性的技术进展之一,也是互连集成技术的解决方案之一.在对互连集成技术中面临的技术与物理挑战的特点和可能的解决途径概括性介绍的基础上,重点介绍和评述了低k介质和Cu的互连集成技术及其所面临关键的技术问题,同时还对三维集成互连技术、RF互连技术和光互连技术等Cu互连集成技术之后的可能的新一代互连集成技术和未来互连技术的发展趋势给予了评述和展望.     

表面波表征ULSI互连布线双层薄膜机械特性的理论计算

利用超声表面波在分层结构中传播的频散特性来测量薄膜的机械特性具有准确、快速、对材料无损伤等突出优点.本文研究了在Si(100)衬底上淀积双层薄膜的分层结构中超声表面波沿Si[110]晶向传播的速度-频率色散关系.应用此方法对超大规模集成电路(ULSI)中具有质软、易碎特点的低介电常数互连介质(low-k)薄膜的机械特性进行了表面波频散计算.研究了先进ULSI互连布线系统中广泛存在的3种分层薄膜结构上表面波的频散特性.计算表明不同分层结构对表面波的频散特性影响很大.对于同一分层结构,表面波的频散曲率随low-k薄膜杨氏模量的减小而显著增大.本工作为准确测定low-k薄膜的杨氏模量提供了理论计算依据.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

Analysis of thermal stresses in copper interconnect/low-k dielectric structures

Numerical simulations of thermal stresses in copper (Cu) interconnect and low-k dielectric systems are carried out. The three-dimensional (3-D) finite-element analysis assumes a two-level metal structure connected by a via. Mechanical deformation is generated by thermal expansion mismatches during cooling and cyclic temperature changes. The thin barrier/etch stop layers, as well as oxide or polymer-based low-k dielectric materials, are all taken into account in the model. The stress and deformation fields are examined in detail; salient features having direct implications in device reliability are illustrated with representative contour plots. It is found that the use of low-k material in place of traditional oxide dielectric significantly reduces the triaxial tensile stresses in Cu but enhances plastic deformation, especially in the via region. The compliant low-k material causes the thin barrier layers to bear very high stresses. Deformation in the Cu line and via structure is more affected by the thermal expansion property of the dielectric, but the stresses in the barrier layers are more influenced by the elastic modulus of the dielectric.     

倒装焊器件中Cu/low-k结构热可靠性分析

利用有限元软件建立了倒装焊器件的整体模型和Cu/low-k结构的子模型,分析了在固化工艺及后续热循环条件下Cu/low-k结构的热机械可靠性。结果表明:在金属互连线与低电介质材料的交界处容易产生可靠性问题,采用low-k材料及铜互连线时均增大了两者所受最大等效应力,另外,通孔宽度对low-k及铜线的热应力影响并不明显。     

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.     

Mechanical integrity evaluation of low-k device with bump shear

The mechanical integrity of low-k dielectric films has brought many process challenges in both front-end integration and back-end assembly, mostly due to possible interfacial delamination and fractures within the low-k films. From a packaging point of view, it is important to have an assessment of the integrity of the low-k stack before the device is fully assembled and the time-consuming full package evaluation is started. Some of the methods that are presently used to evaluate devices with low-k films either do not reflect the real stress situation in a package (such as 4-point bend), or introduce a mixed die-solder failure mode (such as die pull), which makes the results hard to interpret. In this paper, an evaluation method using solder bump shear is introduced. The solder joints are electroplated with a Cu stud as part of the under bump metallization. When the testing parameters are carefully optimized, bump shear can induce a failure in the low-k stack. By analyzing the maximum load of the shear test and the characteristics of the load curves, die with different interlayer dielectric materials and locations on the die with different interconnect metal densities can be effectively differentiated. A finite-element model is established and fracture mechanics methodologies are utilized to interpret the results of the bump shear.