Novel m.o.s. differential amplifier for sampled-data applications

A novel form of differential amplifier is reported which employs a simple, capacitive input differential circuit in place of the conventional differential pair and current source. The amplifier is especially suitable for monolithic integration in an m.o.s. technology, and generates a time-multiplexed, sampled data output signal compatible with many current signal processing techniques.     

High-gain c.m.o.s. cascode operational amplifier

The letter describes a single-stage (> 80 dB) operational amplifer using a complementary cascode configuration. The device is designed for micropower applications.     

Integrated n.m.o.s. operational amplifier for c.c.d. transversal filters

An integrated operational amplifier employing a new high-gain input stage and implemented with n.m.o.s. enhancement devices is reported. The circuit has been designed with reference to the output differential-charge amplifier of a c.c.d. transversal filter. The performance parameters of the amplifier are presented.     

Complementary dynamic m.o.s. logic circuits

Allowing both p and n channel groups of transistors to be blocked between transitions of c.m.o.s. gates leads to complementary dynamic m.o.s. circuits which, in many cases, are significantly less complex than their static counterparts. The value of the concept and a method of synthesis are demonstrated with a practical example. Systematic application to frequency dividers yields very simple new structures.     

Three-valued c.m.o.s. cycling gates

The design of three-valued cycling gates with c.m.o.s. integrated circuits is presented. Circuits for the cycling and the inverse cycling gates prove to be simpler than those previously reported.     

Dynamic amplifiers in c.m.o.s. technology

A biasing scheme for dynamic amplifiers is proposed and several dynamic amplifiers are described. Furthermore, advantages and limitations of dynamic amplifiers are briefly discussed and some experimental results are presented.     

Implementation of 3-valued logic with c.o.s.m.o.s. integrated circuits

Two ternary gates realising basic ternary operators (ternary NOR, NAND and invertors) are designed with c.o.s.m.o.s. integrated circuits. Any one of these gates may be used to implement several 3-valued algebras.     

Realisation of three-valued c.m.o.s. cycling gates

A new design technique for three-valued cycling operators is presented. The new circuits are shown to be simpler than those previously reported.     

Polarisable dielectrics for m.o.s.t.s

The use of a new and polarisable dielectric layer has made it possible to obtain large threshold-voltage shifts in m.o.s. capacitors.     

ZOGMOST: an improved m.o.s.t. for c.c.d. peripheral circuits

An improved formation for m.o.s. transistors fabricated with the `shadow-etch? c.c.d. process is reported. The narrow self-aligned gaps produced by the process are used to provide an additional screen gate, which allows the gate-drain overlap capacitance to be minimised, thereby improving the frequency characteristics of linear and digital m.o.s. circuits. Depending on the gain of the stage involved, an improvement in the frequency performance of up to 5 times is expected, and practical results for the modified m.o.s.t. agree with this prediction.     

Use of a capacitive load in m.o.s. dynamic logic

This letter proposes a new form of integrated m.o.s. dynamic logic based on an invertor comprising a single m.o.s.t. and a load capacitor. A compact digital delay line is described consisting of pairs of invertors operating from two clock phases. The technique is briefly compared with other dynamic approaches.     

Analogue c.c.d. correlator using monolithic m.o.s.t. multipliers

A 32-stage analogue correlator has been hybridised by using a multitapped c.c.d. delay line and m.o.s.t. multipliers fabricated on the same silicon chip. A multiple-port sample?hold system has been adopted for storage of the reference signal, thereby allowing it to be refreshed continuously. The viability of a design for a fully analogue monolithic c.c.d. correlator is established.     

New V-groove double-diffused m.o.s. (v.d.m.o.s.)

A new V-groove double-diffused m.o.s. (v.d.m.o s.) is proposed which combines the V-groove technology and the double-diffused m.o.s. (d.m.o.s.) technology. The fabrication processes arc qualitatively described. The gate is located on the vertical V-shaped surface, and the effective channel length is controlled by the vertical-diffusion process of the double-diffusion step. The v.d.m.o.s. is expected to have a faster speed and higher production yield than the ordinary d.m.o.s.     

Implementation of some ternary operators with c.m.o.s. integrated circuits

A ternary gate which realises the basic operators of two different algebras is designed with c.m.o.s. integrated circuits. Both algebras have been selected because they are associated with powerful minimisation procedures. A delay time of 350 ns may be obtained.     

Implementation of ternary identity cells using c.m.o.s. integrated circuits

Most of the ternary operators recently described are based on the identity cell and realised by c.m.o.s. integrated circuits. Three simpler designs of the identity cell are presented here: the 2-transistor inverter, the improved-speed 6-transistor cell and the all-c.m.o.s. micropower cell using only 12 transistors.     

Two-dimensional solution of the d.c. characteristics for the m.o.s.t.

A method is outlined for the determination of a 2-dimensional solution of the potential distribution in the substrate of the m.o.s.t., based on the complete depletion-neutral approximation. Channel current is derived from a 1-dimensional solution of the continuity equation along the silicon-silicon dioxide interface, for given values of extrinsically applied electrode potentials. Theoretical characteristics have been validated by comparison with those of a practical device. A discussion of pinchoff is also included.     

Depletion m.o.s. power transistors

A new depletion m.o.s. transistor is proposed. The structure uses anisotropic etching to define the channel in an n?p epitaxial silicon slice. The fabrication, characteristics and power capabilities of the device are discussed.     

Design for a high-speed m.o.s. associative memory

An experimental 64-bit m.o.s. associative memory has been developed from a limit-case design study. Speeds in excess of 50 MHz are reported at a cost per bit that could approach eight times that for a conventional m.o.s. dynamic r.a.m. The design of the basic associative memory cell is described.     

Thermal drift of m.o.s. devices

Experimental results concerning the temperature dependence of an m.o.s. field-effect transistor are presented. These results show a striking linear dependence of the temperature coefficient on the gate voltage. Comparison between experiment and simplified theory gives rise to many problems of validity of the theory.