High-performance ultralow-temperature polycrystalline silicon TFT using sequential lateral solidification

This letter presents technologies to fabricate ultralow-temperature (< 150 /spl deg/C) polycrystalline silicon thin-film transistor (ULTPS TFT). Sequential lateral solidification is used for crystallization of RF magnetron sputter deposited amorphous silicon films resulting in a high mobility polycrystalline silicon (poly-Si) film. The gate dielectric is composed of plasma oxidation and Al/sub 2/O/sub 3/ grown by plasma-enhanced atomic layer deposition. The breakdown field on the poly-Si film was above 6.3 MV/cm. The fabricated ULTPS TFT showed excellent performance with mobility of 114 cm/sup 2//V /spl middot/ s (nMOS) and 42 cm/sup 2//V /spl middot/ s (pMOS), on/off current ratio of 4.20 /spl times/ 10/sup 6/ (nMOS) and 5.7 /spl times/ 10/sup 5/ (pMOS), small V/sub th/ of 2.6 V (nMOS) and -3.7 V (pMOS), and swing of 0.73 V/dec (nMOS) and 0.83 V/dec (pMOS).     

High-performance poly-Si TFTs made by Ni-mediated crystallization through low-shot laser annealing

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been fabricated using metal-induced crystallization followed by laser annealing (L-MIC). Laser annealing after MIC was found to yield a major improvement to the electrical characteristics of poly-Si TFTs. At a laser fluence of 330 mJ/cm/sup 2/, the field effect mobility increased from 71 to 239 cm/sup 2//Vs, and the minimum leakage current reduced from around 3.0/spl times/10/sup -12/ A//spl mu/m to 2.9/spl times/10/sup -13/ A//spl mu/m at a drain voltage of 5 V. In addition, the dependence of the TFT characteristics on the laser energy density was much weaker than that for conventional excimer laser annealed poly-Si TFTs.     

A novel germanium doping method for fabrication of high-performance p-channel poly-Si/sub 1-x/Ge/sub x/ TFT by excimer laser crystallization

In this letter, a novel process for fabricating p-channel poly-Si/sub 1-x/Ge/sub x/ thin-film transistors (TFTs) with high-hole mobility was demonstrated. Germanium (Ge) atoms were incorporated into poly-Si by excimer laser irradiation of a-Si/sub 1-x/Ge/sub x//poly-Si double layer. For small size TFTs, especially when channel width/length (W/L) was less than 2 /spl mu/m/2 /spl mu/m, the hole mobility of poly-Si/sub 1-x/Ge/sub x/ TFTs was superior to that of poly-Si TFTs. It was inferred that the degree of mobility enhancement by Ge incorporation was beyond that of mobility degradation by defect trap generation when TFT size was shrunk to 2 /spl mu/m/2 /spl mu/m. The poly-Si/sub 0.91/Ge/sub 0.09/ TFT exhibited a high-hole mobility of 112 cm/sup 2//V-s, while the hole mobility of the poly-Si counterpart was 73 cm/sup 2//V-s.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.     

A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened a-Si active island

A four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 /spl mu/m and a channel width of W = 1.2 /spl mu/m possesses a high field-effect mobility of 260 cm/sup 2//Vs and an on/off current ratio of 2.31 /spl times/ 10/sup 8/.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.     

High-performance RSD poly-Si TFTs with a new ONO gate dielectric

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger Q/sub BD/, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm/sup 2//V/spl middot/s, and an on/off current ratio exceeding 10/sup 8/.     

Polycrystalline silicon films and thin-film transistors using solution-based metal-induced crystallization

Polycrystalline silicon (poly-Si) films consisting of dish-like and wadding-like domains were obtained with solution-based metal-induced crystallization (SMIC) of amorphous silicon. The Hall mobility of poly-Si was much higher in dish-like domains than in wadding-like domains. Thin-film transistors (TFTs) have been prepared using those two kinds of poly-Si films as the active layer, followed by the phosphosilicate glass (PSG) nickel gettering. The field effect mobility of dish-like domain poly-Si TFTs and wadding-like poly-Si TFTs were 70/spl sim/80 cm/sup 2//V/spl middot/s and 40/spl sim/50 cm/sup 2//V/spl middot/s, respectively. With a multi-gate structure, the leakage current of poly-Si TFTs was reduced by 1 to 2 orders of magnitude. In addition, the gate-induced drain leakage current (GIDL) and uniformity of the drain current distribution were also improved. P-type TFTs fabricated using SMIC exhibited excellent reliability.     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

Reduction of off-current in self-aligned double-gate TFT with mask-free symmetric LDD

In this work, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10/sup -9/ A//spl mu/m to 10/sup -12/ A//spl mu/m. The on/off current ratio is increased by three orders of magnitude accordingly from around 10/sup 4/ to 10/sup 7/.     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

Low-resistance ultrashallow extension formed by optimized flash lamp annealing

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 /spl times/ 10/sup 18/ cm/sup -3/ and the sheet resistance of 13 nm and 700 /spl Omega//sq for As and 14 nm and 770 /spl Omega//sq for BF/sub 2/ with junction leakage lower than 1 /spl times/ 10/sup -16/ A//spl mu/m/sup 2/ at 1.5 V were successfully obtained without wafer slip and warpage problems.     

Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing

Pulsed excimer laser annealing (ELA) is used to reduce the poly-Si gate depletion effect (to <0.1 nm). Low resistivity (0.58 m/spl Omega//spl middot/cm) and high active boron concentration (4/spl times/10/sup 20/ cm/sup -3/) at the gate-oxide interface are achieved while preserving the gate oxide quality and avoiding boron penetration, to meet International Technology Roadmap for Semiconductors requirements for sub-65-nm CMOS technology nodes. ELA is compatible with high-/spl kappa/ dielectric (HfO/sub 2/) and results in significantly lower gate leakage current density as compared with rapid thermal annealing (RTA).     

4H-SiC UV photo detectors with large area and very high specific detectivity

Pt/4H-SiC Schottky photodiodes have been fabricated with the device areas up to 1 cm/sup 2/. The I-V characteristics and photoresponse spectra have been measured and analyzed. For a 5 mm/spl times/5 mm area device leakage current lower than 10/sup -15/ A at zero bias and 1.2/spl times/10/sup -14/ A at -1 V have been established. The quantum efficiency is over 30% from 240 to 320 nm. The specific detectivity, D/sup */, has been calculated from the directly measured leakage current and quantum efficiency are shown to be higher than 10/sup 15/ cmHz/sup 1/2//W from 210 to 350 nm with a peak D/sup */ of 3.6/spl times/10/sup 15/ cmHz/sup 1/2//W at 300 nm.