Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D-V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.     

A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

Group III–V ternary compound semiconductor materials for unipolar conduction in tunnel field-effect transistors

A distinct materials combination is presented for tunnel field-effect transistors (TFETs): gallium arsenide phosphide (GaAsP) as a wider-bandgap material in the drain and channel regions with indium gallium arsenide (InGaAs) as a narrow-bandgap material for the source region. The introduction of this novel materials combination greatly improves the ON-state current, OFF-state current, ambipolar behavior, threshold voltage, and subthreshold slope compared with other group III–V ternary heterojunction TFETs. In GaAsP–InGaAs TFETs, the ambipolar current remains equal to the OFF-state current. This paper explores the potential of the proposed device for ultralow-power high-performance applications.     

Simulation of slow current transients and current collapse in GaN FETs

Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V _D is raised abruptly (while keeping the gate voltage V _G constant), the drain current I _D overshoots the steady-state value, and when V _D is lowered abruptly, I _D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V _D and V _G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V _D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.     

Deterioration of device characteristics of MFSFET due to fatigue

Abstract

Change of device characteristics of the metal-ferroelectric-semiconductor FET (MFSFET) with the progress of fatigue of the ferroelectric thin film are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V_G curves exhibit the accumulation, the depletion and inversion regions clearly. They also exhibit the memory window of 2V. I_D-V_D curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I_D-V_D curve is 6mA/cm², which decreases as much as 50% after fatigue. Our model is expected to be very useful in the estimation of the behaviour of MFSFET devices with the progress of fatigue.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

A systematic investigation of the integrated effects of gate underlapping,dual work functionality and hetero gate dielectric for improved performance of CP TFETs

This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of \(\mathrm{SiO}_{2}\) as the gate dielectric. Therefore, a hetero gate dielectric \(\mathrm{SiO}_{2}\) on the drain side and \(\mathrm{HfO}_{2}\) on the source side are considered in order to improve the RF parameters and enhance the ON-current concept, respectively. Finally, the combined effects of gate underlap with work function shift and hetero dielectric are analyzed in CP TFETs. The results show that proper underlap length and gate work function provide a significant improvement in device performance. Therefore, optimization of the underlap length and work function is performed to determine the specific work function that provides overall enhancement of DC and analog/RF performance of the device. In addition, optimization of the dual work function gate length is demonstrated.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

New current–voltage transferring device with different metals

A new concept of an electrical shunt with different materials (aluminum and copper) has been developed to be used as an alternative current measurement device. The device provides better current measurement characteristics compared with the conventional current measurement devices such as a shunt resistor with an ammeter or the multiple shunts consisting of molybdenum having a low temperature coefficient and a Rogowski coil with an integrated circuit. The currents in several electrical circuits have been measured using the developed current–voltage transferring device (CVTD) as voltages between the aluminum and copper elements. The measured voltages (V_m) are proportional to measuring currents (I_m), which is shown as the following the experimental equation V_m [mV] =kI_m [A], in which k is a coefficient depending on the configuration of the CVTD. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Fringing-field-based 2-D analytical model for a gate-underlap double-gate TFET

An analytical model was developed to calculate the potential distribution for a gate-underlap double-gate tunnel FET. The electrostatic potential of the device was derived using the two-dimensional Poisson’s equation, incorporating the fringing electric field in the gate-underlap surface and employing a conformal mapping method. In addition to analytical potential modeling, the electric field and drain current were evaluated to investigate the device performance. Excellent agreement with technology computer-aided design (TCAD) simulation results was observed. The dependence of the ambipolar current on the spacer oxide dielectric constant, spacer length, channel length, and gate material thickness was examined using the proposed model. The effects of the variation of all of these parameters were well predicted, and the model reveals that use of a low-\(\kappa \) spacer dielectric combined with a high-\(\kappa \) gate dielectric results in the minimal ambipolar current for the device.     

Heterogate junctionless tunnel field-effect transistor: future of low-power devices

Gate dielectric materials play a key role in device development and study for various applications. We illustrate herein the impact of hetero (high-k/low-k) gate dielectric materials on the ON-current (\(I_{\mathrm{ON}}\)) and OFF-current (\(I_{\mathrm{OFF}}\)) of the heterogate junctionless tunnel field-effect transistor (FET). The heterogate concept enables a wide range of gate materials for device study. This concept is derived from the well-known continuity of the displacement vector at the interface between low- and high-k gate dielectric materials. Application of high-k gate dielectric material improves the internal electric field in the device, resulting in lower tunneling width with high \(I_{\mathrm{ON}}\) and low \(I_{\mathrm{OFF}}\) current. The impact of work function variations and doping on device performance is also comprehensively investigated.     

Junctionless MOSFETs with laterally graded-doping channel for analog/RF applications

In this paper, we propose a laterally graded-channel pseudo-junctionless (GPJL) MOSFET for analog/RF applications. We examine the dynamical performance of GPJL MOSFET and compare it with the common junctionless (JL) MOSFET architecture using a 2-D full-band electron Monte Carlo simulator (MC) with quantum correction. Our results indicate that the GPJL MOSFET outperforms the conventional JL MOSFET, yielding higher values of drain current (I _ds), transconductance (g _m), and cutoff frequency (f _t). Further, the emerging electric field and velocity distributions, as a consequence of the channel engineering introduced by the GPJL MOSFET, result in lower output conductance (g _ds) and higher early voltage (V _ea). The preeminence of the GPJL transistor over the JL transistor is further illustrated by showing improvements on the intrinsic voltage gain (A _vo) in the subthreshold regime, to as high as 61 %. These results indicate that our proposed GPJL MOSFET yields improvement in the analog/RF performance metrics as compared to JL MOSFETs.     

Design and structural optimization of junctionless FinFET with Gaussian-doped channel

A junctionless (JL) fin field-effect transistor (FinFET) structure with a Gaussian doping distribution, named the Gaussian-channel junctionless FinFET, is presented. The structure has a nonuniform doping distribution across the device layer and is designed with the aim of improving the mobility degradation caused by random dopant fluctuations in JL FinFET devices. The proposed structure shows better performance in terms of ON-current (\(I_{\mathrm{ON}}\)), OFF-current (\(I_{\mathrm{OFF}}\)), ON-to-OFF current ratio (\(I_{\mathrm{ON}}{/}I_{\mathrm{OFF}}\)), subthreshold swing, and drain-induced barrier lowering. In addition, we optimized the structure of the proposed design in terms of doping profile, spacer width, gate dielectric material, and spacer dielectric material.     

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

We report a systematic, quantitative investigation of analog and RF performance of cylindrical surrounding-gate (SRG) silicon MOSFET. To derive the model, a pseudo-two-dimensional (2-D) approach applying Gauss’s law in the channel region is extended for the cylindrical SRG MOSFET. Based on surface potential approach, expressions of drain current and differential capacitances are obtained analytically. Analog/RF figures of merit of SRG MOSFET are studied, including transconductance efficiency g _m/I _d, intrinsic gain, output resistance, cutoff frequency f _T, maximum oscillation frequency f _max and gain bandwidth product GBW. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modeled predictions have been extensively compared with the simulated characteristics obtained from the ATLAS device simulator and a nice agreement is observed with a wide range of geometrical parameters.     

Fabrication and Characterization of Gate-Connected 1T2C-Type Ferroelectric Memory with Paired Bi4 − xLaxTi3O12 Capacitors

A gate-connected 1T2C-type ferroelectric memory, in which the bottom electrodes of paired ferroelectric capacitors are connected to the gate electrode of an underlying FET (field effect transistor) on the field oxide region, was fabricated using a Bi_{4 ? x}La_xTi₃O₁₂ (BLT) film and its electrical properties were characterized. The I_D-V_G (drain current-gate voltage) characteristics of a FET combined with a single ferroelectric capacitor showed that the paired capacitors had almost the same ferroelectric property. It was found in the readout operation that there existed an optimum voltage to maximize the drain current on/off ratio between datum ‘1’ and datum ‘0,’ and that the maximum ratio was as large as 6 × 10⁴. It was also found that the drain current level remained constant, even if the readout operation was repeatedly conducted. It was concluded from these results that the 1T2C-type memory was successfully fabricated using the proposed process and operated properly.     

Modeling gate-all-around Si/SiGe MOSFETs and circuits for digital applications

Apart from excellent electrostatic capability and immunity to short-channel effects, the performance of gate-all-around (GAA) nanowire (NW) metal-oxide-semiconductor field-effect transistors (MOSFETs) can be further enhanced by incorporating strain. Owing to the technological importance of strained GAA (S-GAA) NW MOSFETs in modern electronics, we have proposed an analytical model of the threshold voltage and drain current for S-GAA NW MOSFETs taking into account the appreciable contributions of source (S) and drain (D) series resistances in the nanometer regime, along with quantum mechanical effect. We have focused on the elliptical cross section of the device as is necessary to consider the fabrication imperfections which give rise to such cross section, rather than an ideal circular structure. Incorporating S/D series resistance in the model of drain current demands for algorithms based on multi-iterative technique, which has been proposed in this paper for analyzing the impact of strain, NW width, aspect ratio and so on, on the performance of S-GAA NW devices with emphasis on CMOS digital circuits. Based on our proposed methodology, we have also investigated the scope of using high-k dielectric materials and metal gate in S-GAA NW structures.     

Study of RF Linearity in sub-50 nm MOSFETs Using Simulations

We investigate the linearity performance of dual-gate and fully-depleted silicon-on-insulator MOSFETs through use of 2D computer simulations, which take into account quantum mechanical considerations and non-equilibrium transport effects. We show that DG MOSFET is superior not only in terms of g _m /I _d characteristics, central to analog performance, but also in terms of linearity performance, by up to 5 dBm, in most operating conditions. Linearity figures of devices considered in this work range from ?10 to ?20 dBm, which answer the needs of mobile communication standards currently in use. We also observe that, when properly scaled, bulk MOSFETs display competitive analog performance and have third-order intercept figures very similar to SOI device. We can identify, through simulation experiments, that quantum mechanical effects have positive impact on linearity, while non-equilibrium conditions lower linearity performance. With increasing drain bias, we find that linearity saturates at a moderately low voltage (～1 V) in all devices.     

Integration and characterization of MFISFET using Pb5Ge3O11

Abstract

The first MFIS FETs PMOS using Pt/Pb₅Ge₃O₁₁/ZrO₂/n-Si structure has been successfully fabricated. The PGO thin film was deposited by spin on method. Single phase PGO with strong c-axis orientation and low leakage current was obtained on ZrO₂ substrate. Pt was used as top electrode and the gate stack was dry etched using chlorine chemistry. Using CMOS compatible process, the integration of MFIS FETs is simple and reliable. I_D-V_G and I_D-V_D were characterized on 10 × 10 μrn (L × W) devices. The memory window obtained is about 1.3V with 200nm PGO and 13nm ZrO₂. It is also found that memory window is less dependent on device sizes.     

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with \(\hbox {M}_{1}\) as overlap gate, \(\hbox {M}_{2}\) as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of this structure shows that the lateral ambipolar leakage between channel and drain is reduced by approximately three orders, the OFF-state leakage is reduced by one order, and the \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio is increased by more than one order at \(V_\mathrm{{GS}}=V_{\mathrm{DS}} =1.0\) V as compared to the conventional Si EHBTFET. The performance is improved further by employing asymmetric underlaps (\(\hbox {Lgs}\ne \hbox {Lgd}\)) with double dielectric pockets at source and drain, called as proposed structure 2. The pocket dimensions have been optimized, and an average subthreshold swing of 17.7 mV/dec (25.5% improved) over five decades of current is achieved with an ON current of \(0.23~\upmu \hbox {A}/\upmu \hbox {m}\) (11% improved) in proposed structure 2 in comparison with the conventional EHBTFET. Further, the parasitic leakage paths between overlap/underlap interfaces are blocked and the OFF-state leakage is reduced by more than two orders. A high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\,\hbox {ratio}~>10^{9}\) (two orders higher) is achieved at \(V_{\mathrm{DS}} =V_{\mathrm{GS}} =1.0~\hbox {V}\) in the proposed structure 2 in comparison with the conventional one.