A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing

This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small instruction set processors called mini-cores as well as standard DSP and CPU cores that communicate using message passing. The mini-cores are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occur at the sampling rate only.The mini-cores are intended as soft-macros to be used in the implementation of system-on-chip solutions using a synthesis-based design flow targeting a standard-cell implementation. They are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application. To give an impression of the size of a mini-core we mention that one of the FIR mini-cores in a prototype design has 16 instructions, a 32-word × 16-bit program memory, a 64-word × 16-bit data memory and a 25-word × 16-bit coefficient memory.Results obtained from the design of a prototype chip containing mini-cores for a hearing aid application, demonstrate a power consumption that is only 1.5–1.6 times larger than a hardwired ASIC and more than 6–21 times lower than current state of the art low-power DSP processors. This is due to: (1) the small size of the processors and (2) a smaller instruction count for a given task.     

传统教学方法与多媒体教学方法的相互配合

传统教学方法与现代多媒体教学方法有各自的特点。但在教学中可将这两种方法配合起来使用,使其应相互补充,相得益彰。不能以现代多媒体教学方法去替代传统的教学方法。而应以传统的教学手段为主,以现代多媒体方法为辅。不能把多媒体教学方法留于形式,而要真正发挥计算机的长处,起到传统教学方法无法达到的作用。     

高速Viterbi处理器—流水式块处理并行结构

本文提出一种流水式块处理并行Ｖｉｔｅｒｂｉ处理器，可以得到ＬＭ倍增速（Ｍ为流水级数，Ｌ为块长度），为达到更高速的Ｖｉｔｅｒｂｉ处理器提供了新型的并行结构。它可用Ｓｙｓｔｏｌｉｅ阵列构成，因而适于ＶＬＳＩ实现。     

Architecture Concepts for Multimedia Signal Processing

Architectural concepts are presented aimed at future multimedia processing schemes. Starting from an analysis of current and future multimedia applications, specific computational requirements are derived. It will be shown that multimedia applications benefit from an exhaustive and flexible exploitation of parallelism. Three architectural concepts—reconfigurable computing, simultaneous multithreading, and associative controlling—are presented, and their potential to increase further the performance on future multimedia applications is investigated.     

一种成像光谱数据的分布式处理系统结构

随着成像光谱遥感技术的发展,已获取的大量成像光谱数据需要一种更好的共享、处理模式来满足日益增长的应用处理要求;另一方面,计算机网络技术和分布式计算技术的发展为实现这样的构想提供了基础的技术条件.提出了一种成像光谱数据的Web环境下应用的系统结构.     

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm², and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he was with the NEC Information Technology Research Laboratories, Kawasaki, Japan, working on efficient implementations of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Sören Moch received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1997.Since then he has been Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of processor architectures for image, video and multimedia signal processing applications.Lars Friebe studied electrical engineering at the Universities Ulm and Hannover, Germany. In 1999, he worked at the NEC System ULSI Research Laboratory in Kanagawa, Japan. He received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1999.Since then he has been a Research Assistant with the Laboratory for Information Technology, University of Hannover. His current research interests are in the area of parallel programmable VLSI architectures for real-time image processing.Mark B. Kulaczewski started his studies in electrical engineering at the University of Hannover, Germany. In 1994, he transferred to Purdue University, West Lafayette, USA, and received the M.S. degree in electrical engineering in 1996.Since 1997 he has been a Research Assistant at the Laboratory for Information Technology and the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable real-time architectures for video coding and image segmentation, and instruction-set extensions for cryptographic applications.Sebastian Flügel was born in Crivitz, Germany, in 1975. He received his Dipl.-Ing. degree from the Department of Electrical Engineering of the University of Rostock in 2001.Since then he has been a Ph.D. candidate at the Institute of Microelectronic Systems at the University of Hannover. He works in the field of architectures and systems for video processing systems. His focus is on algorithms for video encoding and the development of optimized hardware architectures.Heiko Klußmann received the Dipl.-Ing. degree in computer engineering from the University of Hannover, Germany, in 2002.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests are in the area of programmable architectures for real-time video signal processing.Andreas Dehnhardt was born in Frankfurt am Main, Germany, in 1976. He received his Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 2002.Since then, he has been a Research Assistant with the Institute of Microelectronic Systems, University of Hannover. His current research interests include programmable architectures for multimedia applications and implementation of real-time MPEG-4 encoding schemes.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1980 and in Summer 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL research center, Stuttgart. Since 1987 he is Professor in the Department of Electrical Engineering, since 2002 in the Department of Computer Science at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002. His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

A methodological framework for performance estimation of multimedia signal processing applications on different implementation platforms is presented. The methodology derives a complexity profile which is characteristic for an application, but completely platform-independent. By correlating the complexity profile with platform-specific data, performance estimation results for different platforms are obtained. The methodology is based on a reference software implementation of the targeted application, but is, in constrast to instruction-level profiling-based approaches, fully independent of its optimization degree. The proposed methodology is demonstrated by example of an MPEG-4 Advanced Simple Profile (ASP) video decoder. Performance estimation results are presented for two different platforms, a specialized VLIW media processor and an embedded general-purpose RISC processor, showing a high accuracy of he methodology. The approach can be employed to assist in design decisions in the specification phase of new architectures, in the selection process of a suitable target platform for a multimedia application, or in the optimization stage of a software implementation on a specific platform.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he worked at the NEC Information Technology Research Laboratories, Kawasaki, Japan, on efficient implementation of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization approaches for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL Research Center, Stuttgart, Germany. Since 1987 he is Professor in the Department of Electrical and Computer Engineering at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002.His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Dr. Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

基于内容的多媒体信息检索

较系统地介绍了基于内容的多媒体检索技术。对于基于内容的视频检索技术，介绍了基于内容的视频处理、视频检索的方式和ML算法在视频检索中的应用。此外，还介绍了基于内容的压缩方法MPEG-4、MPEG-7、MPEG-21等。     

信息处理用现代维吾尔语词干词类标记集研究

阐述了研究与制定"现代维吾尔语词干词类标注标记集"必要性,讨论只靠语法角度提出的一类词干"现代维吾尔语词干词类标注标记集"有限性;论述了通过吸收国内外英语、汉语层次分析研究的最新成果,结合现代维吾尔语词干的本身特点研究现代维吾尔语词干语法语义分类体系迫切性;讨论信息处理用现代维吾尔语一类、二类、三类和四类词干词类标记规范。     

IA指令集仿真器的优化设计与实现

指令集仿真器是现代处理器设计和软件设计过程中不可缺少的一部分。指令集仿真器不仅有助于验证处理器和编译器的设计功能和性能,还能用来评估体系结构设计是否合理。现在指令集仿真器的广泛使用已经成为与此相关的软件设计的基础。为了得到高速的指令集仿真器,介绍了优化指令集仿真器的理论基础,在此基础之上提出了一系列优化方法,并采用ARM7处理器进行了逐一验证并取得了明显成效。     

基于C40阵列图象处理系统结构的研究

本文给出了-基于C40DSP的新颖阵列图象处理系统．该阵列采用了全局互连网络和局部互连网络，构成了一分布式存贮器体系和共享存贮器体系相结合的存贮器体系结构．理论研究表明，阵列处理器的性能有了明显的改善．阵列处理器的最大峰值指标可达：800MFLOPS、4．4BOPS和22．4Gbits／s．     

一款DSP指令集模拟器性能优化技术研究

文中研究和设计的指令集模拟器(Instruction Set Simulator,ISS)仿真了"中微一号"(ZW100)DSP指令系统和存储器系统行为。在现代嵌入式系统设计过程中,ISS能够在硬件原型构造出来之前,完成对处理器设计的正确性验证和性能分析工作;同时,其还可用于验证操作系统、编译器、汇编器、连接器等系统软件的正确性和各项性能指标。目前,国内外对ISS的研究主要集中在保证ISS灵活性的前提下,应用各种优化技术,提升它的指令仿真执行速度。文章在吸收借鉴目前国际上关于ISS性能优化技术的基础上,通过对仿真策略、仿真内存管理、二进制指令译码算法进一步优化,提高了ISS的整体性能。实验证明,文中提出的优化技术能够有效提升ISS的性能。     

电子侦察中的信号处理方法体系

电子侦察采用截获信号分析的手段,获取电子干扰和情报侦察所需要的信息。随着数字化和软件化的发展趋势,数字信号处理必定在其中发挥十分重要的作用。近年来,电子侦察技术的进步在很大程度上体现在信号处理技术上。简要地综述了在电子侦察中所使用的信号处理方法的基本思路和手段,试图论述其方法体系,并提出一些观点和评述。     

基于指令集随机化的XSS检测和防御系统

针对Web遭受跨站脚本攻击越来越严重的问题,设计了一个基于指令集随机化的服务器端XSS检测和防御模型,并在PhpBB网络论坛系统中进行了实现,通过对实验结果的分析可知,本系统可以很好地检测和防御反射型XSS攻击和存储型XSS攻击,同时能检测和防御因网络或操作系统层漏洞导致的网页篡改和网页挂马等恶意攻击行为。     

激光加工技术在土木-建筑工程中的应用及展望

分析综述了近年来国内外土木-建筑领域激光加工技术的研究状况,适用范围,出现的问题和解决办法,指出和预测了该技术在这一行业的发展方向和应用前景。     

基于P2P架构和SIP协议的多媒体邮件网络研究

文中提出了一种在P2P架构上的基于SIP协议的多媒体邮件网络,他可以克服IP网络上的服务器瓶颈问题和H.323协议的繁琐及低效率问题.同时介绍了本网络采用该P2P架构和SIP协议的优势所在.在此基础上,还介绍了本网络如何对多媒体信息流的获取、存储管理以及播放.最后,对各个功能模块进行了总体介绍.     

The Architecture and Development Flow of the S5 Software Configurable Processor

A software configurable processor (SCP) is a hybrid device that couples a conventional processor datapath with programmable logic to allow application programs to dynamically customize the instruction set. SCP architectures can offer significant performance gains by exploiting data parallelism, operator specialization and deep pipelines. The S5000 is a family of high performance software configurable processors for embedded applications. The S5000 consists of a conventional 32-bit RISC processor coupled with a programmable Instruction Set Extension Fabric (ISEF). To develop an application for the S5 the programmer identifies critical sections to be accelerated, writes one or more extension instructions as functions in a variant of the C programming language, and accesses those functions from the application program. Performance gains of more than an order of magnitude over the unaccelerated processor can be achieved.

VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance

This paper presents the architectural design of a multicomputer interconnection network based on the use of optical technology. The performance of the system is evaluated on a set of signal processing applications. The interconnect uses Vertical Cavity Surface Emitting Lasers (VCSELs) and flexible fiber image guides to implement a physical ring topology that is logically configured as a multiring. Processors in the multicomputer are nodes on the ring and extremely high communication bandwidth is possible. Using the Laser Channel Allocation (LCA) algorithm and the Deficit Round Robin (DRR) media access protocol, the bandwidth available in the optical interconnect can be reconfigured to make efficient use of the interconnect resources. A discrete-event simulation model of the interconnect is used to examine performance issues such as throughput, latency, fairness, and the impact of reconfigurability.Roger D. Chamberlain completed the degrees BSCS and BSEE in 1983, MSCS in 1985, and DSc (computer science) in 1989 all from Washington University in St. Louis, Missouri. He is currently an Associate Professor of Computer Science and Engineering at Washington University, where he is Director of the Computer Engineering Program. Dr. Chamberlain teaches and conducts research in the areas of computer architecture, parallel computing, embedded systems, and digital design.Mark A. Franklin received his BA, BSEE and MSEE from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently a Professor in the Department of Computer Science and Engineering at Washington University in St. Louis, Missouri, and holds the Hugo F. and Ina Champ Urbauer Chair in Engineering. He founded and is former Director of the Computer and Communications Research Center.Dr. Franklin is a Fellow of the IEEE and a member of the ACM. He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chair of the ACM SIGARCH (Special Interest Group on Computer Architecture). His research areas include computer and systems architecture, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation.Praveen Krishnamurthy received the Bachelor of Engineering degree from University of Madras (India) in 2000 and the MS degree in Computer Engineering from Washington University in St. Louis, Missouri, in 2002. He is currently a doctoral student at Washington University in St. Louis.Abhijit Mahajan received his B.E (Electronics) degree from University of Mumbai in 1998. He received is MSEE from Washington University in 2000. He is presently working with Broadcom Corporation in India. His main area of work is signal integrity and systems engineering.     

一种电机FOC算法DSP系统设计及实现

本文设计了一种适用于电机矢量控制算法的数字信号处理系统的微架构定义,包括其指令集定义、存储器模型以及与主CPU的交互模式.该设计具有通过固定部分多操作数有效缩减指令编码长度提高代码密度以及后台执行多周期指令提高ALU并行效率的显著优点.文中给出了典型的FOC控制算法在DSP （Digital Signal Processor）指令集上实现的指令周期数,也给出了对应架构的电路实现情况,最终以ARM CORTEX-M0及几款主流DSP作为比较基线,通过实测实验数据证明了体系结构的高能效比,以较为有限的电路面积代价,极大提高了集成DSP的嵌入式系统的运行效率.