基于内存模型的Java并发编程

多核处理器为并发编程打开了一扇扇新的大门，Java内置的多线程机制可以方便地实现多个并发程序的开发以及多任务同时执行，但是Java线程之间的通信对程序员完全透明，内存可见性问题很容易困扰Java开发人员，本文将简单分析基于内存模型的Java并发编程。     

变电站内IED嵌入式Internet接入技术研究

以嵌入式Internet技术为基础，阐述如何实现变电站内的IED(Intelligent Electrical Device)嵌入式Internet接入，重点讨论了接入模式，实现方法和实时性能。同时，对变电站内的IED嵌入式Internet接入后而引起的网络安全问题及应采取安全策略进行了探讨。     

数字电视接收终端实时数据库的实现

介绍了专用于数字电视接收终端的嵌入式数据库系统，描述了基于主内存数据库的数据检索，物理配置，事务管理机制和并发控制等关键技术，并根据数字电视接收终端的实时环境要求设计了相应的事务调度算法和加锁控制技术。     

嵌入式内存数据库持久性策略研究

针对嵌入式内存数据库系统的数据持久性需求,对现有数据库系统持久性保证策略进行了分析,并根据嵌入式系统和全内存存储环境的特点,提出了嵌入式内存数据库系统的数据库备份和恢复策略,为研制具有持久性的嵌入式内存数据库提供了指引。     

嵌入式系统Java的变革

嵌入式系统的开发者们反映当前的Java既大又慢,稳定性也不好。对于嵌入式的应用其功能也不很完完据SunMicrosystems公司估计,现有40万开发者在使用Java,也己经有人将Java用于嵌入式系统的开发。现行的Java技术规范已包括了EnterpriseJava,PersonalJava和EmbeddedJava,这些规范并没有错,对于上述的不满意究其原因在于它们的实现,特别是涉及嵌入式的PersonalJava和EmbeddedJava缺乏活力。走近JavaSunMlcrosystems1995年首次推出Java语言,其理想的运行环境是Internet上的应用。在此之前,网络主要用于连接巨型机和存储信息的…     

JAVA线程机制在FTP客户端程序中的应用

为使程序具有更好的交互性，通常采用多线程机制。Java程序设计语言将线程支持与语言运行环境结合在一起，使多线程应用程序的开发变得更加容易。本重点讲述了Java的线程机制在FTP客户端程序中的应用。     

Java:不仅仅是一门语言

如果询问工程师们在嵌入式计算机语言方面有什么偏好的话,Java很有可能不会出现在他们开列的清单中.这意味着他们已经错过了利用某种出色的面向对象的开发"环境"的机会,这种环境所提供的精细的内存管理、严格的类型检查和安全功能正是C和C 等语言所缺乏的.     

嵌入式Linux在工业控制领域中的应用

针对嵌入式网络设备的应用特点，介绍嵌入式linux的主要技术及在工业控制领域中的应用。结合硬件平台详细说明嵌入式linux系统的主要实现方法，涉及嵌入式实时内核、内存机制和文件系统的设计。     

产品之窗

Phar Lap Software公司的TNT嵌入式ToolSuite版本8是一种实时开发系统,可供那些想用标准32位编译器和工具编制基于ROM或闪速存储器的嵌入式程序使用.采用TNT嵌入式Toolsuite编制的嵌入式应用程序可在任何一个基于Intel 386/486/Pentium处理器的系统上运行.TNT嵌入式ToolSuite实时版包括Phar Lap开发的实时核心,可支持线程、优先调度和线程间通信.     

基于Java的网络编程及多线程同步机制

介绍Java的网络编程基础，说明了线程的几个状态间的相互转换，对Java的多线程的同步机制和线程间通信机制作了分析，并结合创建一个远程文件服务器的实例，来探讨Java的网络编程对多线程同步机制的支持。     

On the Utilization of Java Technology in Embedded Systems

Java technology has seen an impressive growth in popularity since its introduction in 1995. Although ithas foremost proved its usefulness in the Internet domain, powerful marketactors are currently moving Java into the embedded systems domain. In thisarticle we identify major design issues in embedded systems, and analyze thesuitability of Java technology in such systems. We find that Java technologycan contribute to the embedded system design process on a system level byfacilitating higher run-time reliability and the technology can simplify maintenanceof the product throughout its life cycle. In addition, programmer efficiencyand productivity may be improved, especially for web based applications anddistributed embedded systems.     

Embedded and real-time Java

Embedded and real-time system design are properly separate concerns. Many embedded systems lack strict timeliness requirements, while many real-time systems (e.g., telephone central office switches) are not embedded. However, a number of embedded systems do have real-time requirements, including a number of products that fall under the I&M umbrella. The author addresses both real-time and embedded Java initiatives     

Design of a system software based on a Java SoC processor

Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) middle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to experimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented.     

Enable pervasive computing with Java

The Green Project created Java specifically for an embedded device, a handheld wireless PDA (persnal digital assistant) that was never released as a product. However, Java was launched as a new Internet language. Over time, it became popular for building desktop applications, Web services, and ubiquitous systems, partly because of its "write once, run anywhere" promise. There's no doubt that Java and PDAs are a powerful combination. In Java Development on PDAs: Building Applications for PocketPC and Palm Devices, the author writes that Java developers often have a preconception that having to choose a hardware platform is a concern of the past, since Java runs on any platform. The author discusses portability issues between the PocketPC and PalmOS devices.     

Java technology comes to real-time applications

The Java language provides many benefits to application developers, including memory access safety, platform portability, and very high levels of productivity. However, some of the very Java language features that bring these benefits, such as the garbage collector, have also made it difficult or impossible to create applications with bounded response time characteristics. Implementations of the real-time specification for Java (RTSJ) are now available that have proven to be capable of supporting all aspects of real-time systems. This paper discusses the principal concepts underlying the RTSJ, use of the RTSJ's features in real-time applications, the most critical considerations that must be addressed by RTSJ-compliant Java virtual machine implementers, and two example RTSJ-compliant application designs that can fully utilize the RTSJ to portably support their performance requirements.     

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis

We address the problem of code generation for embedded DSP systems. In such systems, it is typical for one or more digital signal processors (DSPs), program memory, and custom circuitry to be integrated onto a single IC. Consequently, the amount of silicon area that is dedicated to program memory is limited, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints, which may include hard real-time constraints. Unfortunately, existing compiler technology is unable to generate dense, high-performance code for DSPs since it does not provide adequate support for the specialized architectural features of DSPs. These specialized features not only allow for the fast execution of common DSP operations, but they also allow for the generation of dense assembly code that specifies these operations. Thus, system designers often hand-program the embedded software in assembly, which is a very time-consuming task. In this paper, we focus on providing compiler support for one particular specialized architectural feature, namely the paged absolute addressing mode – this feature is found in two commercial DSPs, the Texas Instruments' TMS320C25 and TMS320C50 fixed-point DSPs; however, it may also be featured in application-specific processors (ASIPs). We present some machine-dependent code optimizations that improve code density by exploiting this architectural feature. Experimental results demonstrate that for a set of typical DSP benchmarks, some of our optimizations reduce overall code size and data memory consumption by an average of 5.0% and 16.0%, respectively. Our experimental vehicle throughout this research is the TMS320C25.     

Fractional Rate Dataflow Model for Efficient Code Synthesis

Automatic code synthesis from dataflow program graphs is a promising high-level design methodology for rapid prototyping of multimedia embedded systems. Memory efficient code synthesis from dataflow models has been an active research subject to reduce the gap in terms of memory requirements between the synthesized code and the hand-optimized code. However, existent dataflow models have inherent difficulty of efficiently handling data structures. In this paper, we propose a new dataflow extension called fractional rate dataflow (FRDF) in which fractional number of samples can be produced and consumed. In the proposed FRDF model, a constituent data type is considered as a fraction of the composite data type. Existent integer rate dataflow models can be easily extended to incorporate the fractional rates without loosing analytical properties. In this paper, the SDF model is extended to include FRDF, which can reduce the buffer memory requirements significantly, up to 70%, for some multimedia applications. Extended SDF model with fractional rate has been implemented in our system design environment called PeaCE(Ptolemy extension as Codesign Environment).     

Active memory processor: a hardware garbage collector for real-time Java embedded devices

Java possesses many advantages for embedded system development, including fast product deployment, portability, security, and a small memory footprint. As Java makes inroads into the market for embedded systems, much effort is being invested in designing real-time garbage collectors. The proposed garbage-collected memory module, a bitmap-based processor with standard DRAM cells is introduced to improve the performance and predictability of dynamic memory management functions that include allocation, reference counting, and garbage collection. As a result, memory allocation can be done in constant time and sweeping can be performed in parallel by multiple modules. Thus, constant time sweeping is also achieved regardless of heap size. This is a major departure from the software counterparts where sweeping time depends largely on the size of the heap. In addition, the proposed design also supports limited-field reference counting, which has the advantage of distributing the processing cost throughout the execution. However, this cost can be quite large and results in higher power consumption due to frequent memory accesses and the complexity of the main processor. By doing reference counting operation in a coprocessor, the processing is done outside of the main processor. Moreover, the hardware cost of the proposed design is very modest (about 8000 gates). Our study has shown that 3-bit reference counting can eliminate the need to invoke the garbage collector in all tested applications. Moreover, it also reduces the amount of memory usage by 77 percent.     

An Enhanced Decision-Making Fault Detection Model in Medical IoT Embedded Systems

Wireless Personal Communications - In the Internet of Things (IoT) embedded systems, error-detecting code methods are used to predict fault detection in a data block. Applying an error-detecting...