A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS

This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430×240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146×186 μm2 and consumes 5.3 mW power.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A 3 Gb/s transmitter with a tapless pre-emphasis CML output driver

A 3 Gb/s wireline transmitter (Tx) with a tapless pre-emphasis current-mode logic output driver is presented in this paper. The proposed output driver can support 2.5, 6 and 10 dB pre-emphasis without any additional current tap. It can reduce the current consumption of the output driver by 30 %. The 1.5 GHz phase-locked loop (PLL), multi-phase generator, and 26-to-1 serializer are utilized to serialize 26-bit parallel data to 1-bit 3 Gb/s serial data stream. The rms and peak-to-peak jitters of PLL are 2.97 and 22.5 ps, respectively. The eye opening of the proposed output driver at 3 Gb/s is 0.8UI with a 10 dB loss channel. The current consumption of the output driver is only 5.14 mA, and the Tx is 9 mA. The area of the Tx is 0.72 mm² using the 0.11 μm CMOS process.     

Two-Dimensional Optical Interconnection Based on Two-Layered Optical Printed Circuit Board

The demonstration of an optical platform based on an optical printed circuit board (OPCB) was shown for two-dimensional (2-D) chip-to-chip optical interconnection. The optical platform was designed for 96 Gb/s total throughput which was 2 layers times 4 channels times 4 parallel links times 3 Gb/s/ch and using a passive assembly technology. We fabricated three main components for the 2-D optical interconnection; two-layered six-channel fiber- and connector-embedded OPCB, two-layered six-channel 90deg-bent fiber connectors, and 2-D optical transmitter/receiver (Tx/Rx) modules. The total optical loss from the Tx to the Rx was measured to approximately be -5.3 dB. The optical interconnection using an optical platform was successfully achieved with 3-Gb/s/ch data transmission     

Frequency-Division Bidirectional Communication Over Chip-to-Chip Channels

Frequency division multiple access is applied to bidirectional communication over chip-to-chip links. Frequency division is implemented by dividing the spectrum into low-frequency (dc) and high-frequency (ac) bands using a simple LC filter. The nonidealities that this filter introduces are compensated for with a transmitter/receiver pair that can recover signals in both bands. The receiver uses a dual-path topology that includes hysteresis to recover data from a signal with no dc content. The transmitter is a 6-tap (FIR) pre-emphasis equalizer with variable tap spacing. In simulation, the transmitter and receiver simultaneously communicate error-free at 8 Gb/s over the ac channel and at 500 Mb/s over the dc channel. Measurements shows that the ac and dc signals can be individually recovered and that the two signals occupy distinct frequency bands.      

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10/sup -15/ and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.     

一种6.25 Gb/s带预加重结构的低压差分发送器

采用SMIC 40 nm CMOS工艺,设计了一种带预加重结构的低压差分(LVDS)发送器。低压差分驱动器采用双运放反馈控制电路,可稳定输出信号的摆幅。采用边沿检测电流注入的预加重电路,对输出进行高频预加重,克服了数据高速传输中高频信号的损失。该发送器的速率为6.25 Gb/s,输出差分信号摆幅为300 mV,预加重比例为3.5 dB,功耗为7.1 mW。该低压差分发送器可应用于高速IO物理层电路中。     

一种针对MCM互连的10 Gbit·s-1自适应收发器

均衡和预加重方法是实现MCM高性能收发器的关键。文中采用MCM互连的四端口[WTHX]S[WT5"BZ]参数传输线模型获得了信号衰减分布规律。在此基础上,采用0.13 μm CMOS工艺,设计了一种基于MCM互连的高速收发器:发送端采用二阶预加重技术提高了信号高频分量的增益,并通过高速CML驱动电路发送数据;接收端采用连续时间线性均衡器和基于LMS算法的自适应均衡器。仿真结果表明,该结构的MCM收发器完成了对10 Gbit·s^-1随机信号的收发,补偿了高达-30 dB的互连损耗,并消除了码间干扰(ISI),总功耗仅为23.3 mW。     

A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage.The receiver occupies 300×500/μm2.With the novel half rate period calibration clock data recovery(CDR)circuit,the receiver consumes 52 mW power.The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE).     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.     

Optical Interconnection Platform Composed of Fiber-Embedded Board, 90$^{circ}$-Bent Fiber Block, and 10-Gb/s Optical Module

An architecture of a passively assembled optical platform is suggested for a chip-to-chip optical interconnection system. The platform is constructed using all-fiber media for the optical paths: a fiber-embedded optical printed-circuit board (OPCB) and 90-bent fiber connector. The passive assembling was achieved by employing the guide pins/holes of commercialized ferrules in the optical link between the OPCB, 90-bent fiber connector, and the transmitter/receiver (Tx/Rx) module. From this interconnection scheme, a low total optical loss of was obtained. From an assembled platform with 10 Gb/s/ch 4 ch Tx/Rx modules, a 7-Gb/s/ch data transmission was demonstrated with a bit error rate below , involving the optical and electrical crosstalk arisen in the whole channel operation.     

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s.     

A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75 $Omega$ Coaxial Cable

A fully differential 40-Gb/s cable driver with adjustable pre-emphasis is presented. The circuit is fabricated in a production 0.18 mum SiGe BiCMOS technology. A distributed limiting architecture is used for the driver employing high-speed HBTs in the lower voltage predriver, and a high-breakdown MOS-HV-HBT cascode, consisting of a 0.18 mum n-channel MOSFET and a high-voltage HBT (HV-HBT), for the high voltage output stages. The circuit delivers up to 3.6 V peak-to-peak per side into a 75 Omega load with variable pre-emphasis ranging from 0 to 400%. S-parameter measurements show 42 dB differential small-signal gain, a 3-dB bandwidth of 22 GHz, gain peaking control up to 25 dB at 20 GHz and input and output reflection coefficients better than -10 dB up to 40 GHz. Additional features of the driver include output amplitude control (from 1 V_pp to 3.6 V_pp per side), pulse-width control (35% to 65%) and an adjustable input dc level (1.1 V to 1.8 V) allowing the circuit to interface with a SiGe BiCMOS or MOS-CML SERDES. The transmitter is able to generate an eye opening at 38 Gb/s after 10 m of Belden 1694 A coaxial cable which introduces 22 dB of loss at 19 GHz. Measurement results also demonstrate that the transmitter IC operates as a standalone equalizer for 10-Gb/s data transmission over 40 m of Belden cable without the need for receiver equalization.     

A Single-Chip CMOS-Based Parallel Optical Transceiver Capable of 240-Gb/s Bidirectional Data Rates

We report here on the design, fabrication, and high-speed performance of a parallel optical transceiver based on a single CMOS amplifier chip incorporating 16 transmitter and 16 receiver channels. The optical interfaces to the chip are provided by 16-channel photodiode (PD) and VCSEL arrays that are directly flip-chip soldered to the CMOS IC. The substrate emitting/illuminated VCSEL/PD arrays operate at 985 nm and include integrated lenses. The complete transceivers are low-cost, low-profile, highly integrated assemblies that are compatible with conventional chip packaging technology such as direct flip-chip soldering to organic circuit boards. In addition, the packaging approach, dense hybrid integration, readily scales to higher channel counts, supporting future massively parallel optical data buses. All transmitter and receiver channels operate at speeds up to 15 Gb/s for an aggregate bidirectional data rate of 240 Gb/s. Interchannel crosstalk was extensively characterized and the dominant source was found to be between receiver channels, with a maximum sensitivity penalty of 1 dB measured at 10 Gb/s for a victim channel completely surrounded by active aggressor channels. The transceiver measures 3.25times5.25 mm and consumes 2.15 W of power with all channels fully operational. The per-bit power consumption is as low as 9 mW/Gb/s, and this is the first single-chip optical transceiver capable of channel rates in excess of 10 Gb/s. The area efficiency of 14 Gb/s/mm² per link is the highest ever reported for any parallel optical transmitter, receiver, or transceiver reported to-date.     

A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS

This paper describes a 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications. The transceiver employs a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, software-controlled clock and data recovery (CDR) and adaptive equalization within the receiver, and a novel PLL-based phase rotator for the CDR. The design can operate with channel attenuation of -15 dB or greater at a bit-error rate of 10^-15 or less, while consuming less than 2.25 mW/Gb/s per transceiver.     

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-μm CMOS

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mW. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2dB. Differential group delay of 100 ps can also be tolerated     

A V-band front-end with 3-D integrated cavity filters/duplexers and antenna in LTCC technologies

This paper presents a compact system-on-package-based front-end solution for 60-GHz-band wireless communication/sensor applications that consists of fully integrated three-dimensional (3-D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication, and testing of V-band (receiver (Rx): 59-61.5 GHz, transmitter (Tx): 61.5-64 GHz) transceiver front-end module using multilayer low-temperature co-fired ceramic technology. Vertically stacked 3-D low-loss cavity bandpass filters are developed for Rx and Tx channels to realize a fully integrated compact duplexer. Each filter exhibits excellent performance (Rx: IL<2.37 dB, 3-dB bandwidth (BW) /spl sim/3.5%, Tx: IL<2.39 dB, 3-dB BW /spl sim/3.33%). The fabrication tolerances contributing to the resonant frequency experimental downshift were investigated and taken into account in the simulations of the rest devices. The developed cavity filters are utilized to realize the compact duplexers by using microstrip T-junctions. This integrated duplexer shows Rx/Tx BW of 4.20% and 2.66% and insertion loss of 2.22 and 2.48 dB, respectively. The different experimental results of the duplexer compared to the individual filters above are attributed to the fabrication tolerance, especially on microstrip T-junctions. The measured channel-to-channel isolation is better than 35.2 dB across the Rx band (56-58.4 GHz) and better than 38.4 dB across the Tx band (59.3-60.9 GHz). The reported fully integrated Rx and Tx filters and the dual-polarized cross-shaped patch antenna functions demonstrate a novel 3-D deployment of embedded components equipped with an air cavity on the top. The excellent overall performance of the full integrated module is verified through the 10-dB BW of 2.4 GHz (/spl sim/4.18%) at 57.45 and 2.3 GHz (/spl sim/3.84%) at 59.85 GHz and the measured isolation better than 49 dB across the Rx band and better than 51.9 dB across the Tx band.     

A 10 Gb/s BiCMOS adaptive cable equalizer

A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.