Terminal-oriented model for merged transistor logic (MTL)

A simple device model is derived to represent merged transistor logic (MTL) circuit behavior. Using the Ebers-Moll equations, the proper definitions of the various current gains are derived, and it is shown that MTL devices can be basically interpreted as n-p-n transistors having an additional base current source. The relations between the intensity of this source and the current actually supplied are derived. Time behavior is modeled according to the charge control concept. Using this model, circuit delays are given as a function of current gains, collector and emitter time constants, supply current, and of fan-out.     

An analysis and the fabrication technology of the lambda bipolar transistor

A new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, which is called the Lambda bipolar transistor, is studied both experimentally and theoretically. The principal operation of the Lambda bipolar transistor is characterized by the simple circuit model and device physics. The important device properties such as the peak voltage, the peak current, the valley voltage, and the negative differential resistance, are derived in terms of the known device parameters. Comparisons between the characteristics of the fabricated devices and the theoretical model are made, which show that the analysis is in good agreement with the observed device characteristics.     

An investigation of the intrinsic delay (speed limit) in MTL/I/SUP 2/L

Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. The injection model is used, into which new charge storage parameters are introduced. The majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. A device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

A new high-power voltage-controlled differential negative resistance device—The lambda bipolar power transistor

A new high power voltage-controlled differential negative resistance device using the LAMBDA bipolar transistor structure, called the LAMBDA bipolar power transistor, is proposed and studied. The basic structure of this new device consists of the simultaneous integration of an interdigitated bipolar junction transistor and a merged metal-oxide-semiconductor field effect transistor. Two basic interconnection configurations of the integrated devices are also discussed. Several interesting applications based on the fabricated devices are also demonstrated. It is shown that the proposed device can be used as power signal generator and amplitude modulator using very simple circuits.     

An investigation of the intrinsic delay (speed limit) in MTL/I2L

This paper identifies and analyzes the main mechanisms that determine the intrinsic delay (speed limit) of today's MTL/I²L devices. Experimental devices have been fabricated with different epitaxial thicknesses to find out to what extent the charge storage can be reduced by shallow epitaxy. Such a shallow-epitaxy device is investigated using computer simulation. Hereby, the injection model is used, into which new charge storage parameters are introduced. According to the analysis, the majority of the stored mobile charge is associated with the bottom junction of the n-p-n transistor part, while the charges in the p-n-p's intrinsic base are minor. However, the lateral p-n-p transistor contributes to the intrinsic delay by its high-level-injection current gain falloff. Furthermore, the significance of high intrinsic base sheet resistance of the n-p-n transistor for high speed is pointed out. Using the insight gained, a device is laid out that assumes only existing technologies, yet in the simulation yields intrinsic delays as low as 2 ns for a fan-out of 4.     

Transit Time of Junction Transistors at High Bias Currents†

A study is made of the behaviour of the small-signal base transit time of a transistor at high bias current levels, where increase of transit time occurs due to collector depletion layer contraction in combination with high level injection effects in the base. Computation of theoretical current dependence of transit time is carried out for devices of single-diffused base grading with alloyed emitter and collector junctions. A physical model of the devices, involving exponential base impurity density grading, is used as a basis of analysis. The physical parameters of this model are determined specifically for the transistor samples under study by interpretation of measured terminal properties under low-level injection conditions. Very close agreement between measured and computed dependence of base transit time on d. c. bias current is obtained, subject to appropriate allowance, in analysis, for variation of the operating temperature of the device with d. c. bias condition.     

Optimizing the match in weakly inverted MOSFET's by gated lateralbipolar action

The on-chip n-type MOSFET current mirror circuit with different drawn gate widths and lengths has been fabricated, and has been characterized across the wafer with back gate slightly forward biased. The weakly inverted MOSFET device with a small back-gate forward bias represents equivalently the high-gain gated lateral bipolar transistor in low-level injection. Experimental results have exhibited a substantial improvement in the match of the drain current in weak inversion due to action of the gated lateral bipolar transistor, especially for the small size devices. The extensively measured mismatch of the weak inversion drain current has been successfully reproduced by an analytic statistical model with back-gate forward bias and device size both as input parameters. The experimentally extracted variations in process parameters such as the flat-band voltage and the body effect coefficient each have been found to follow the inverse square root of the device area. The mismatch model thus can serve as a quantitative design tool, and has been used to optimize the trade-off between the device area and the match with the forward back-gate bias as a parameter     

Superintegrated voltage clamp

A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device. Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads. Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers.     

Steady state and transient analysis of SFIIL

Steady state and transient analyses of substrate fed integrated injection logic (SFIIL) have been carried out using an injection model simply by merging all parallel diodes into a single composite diode. The upward gain of the NPN transistor, vertical PNP transistor gain and extrinsic delay of SFIIL devices have been computed for various device areas, junction depths and doping concentrations.     

Characterization and modeling of avalanche multiplication in HBTs

The accurate modeling of weak avalanche breakdown of HBTs in compact bipolar transistor models for circuit simulation is presented. Based on various device electrical characteristics that are grouped into three classes, a modified VBIC avalanche multiplication model is proposed. By simply replacing one constant avalanche model parameter with current linear dependence, the new model predicts well broad behaviors of breakdown from weak avalanche up into high level injections.     

Design, fabrication and operation of a hot electron resonant tunneling transistor

Transistors employing resonant tunneling injection of hot electrons into a thin quantum well base region have been fabricated. The base region in these transistors is formed by a narrow bandgap material like InGaAs so that the first level is a confined one lying below the Fermi level in the contact regions. This results in charge transfer into the bound state in the quantum well thus allowing independent control of the base electrostatic potential. Theoretical calculations showing the importance of various device parameters in the design of a resonant tunneling transistor are presented and preliminary results showing the capability of transistor action in such devices are presented.     

Correlation of diffusion process variations with variations in electrical parameters of bipolar transistors

In this paper we consider the problem of determining the effects of a nonuniformity in diffusion processes on the resultant electrical characteristics in semiconductor devices. A bipolar, planar silicon p-n-p transistor is considered as an example. A model is presented describing the current gain in terms of measurable diffusion parameters. These parameters are 1) the four-point probe reading of the diffused base, 2) the emitter-base junction depth, and 3) the collector-base junction depth or √Dt of the base. The model is used to predict the sensitivity of current gain to each of these diffusion parameters; it is shown that the sensitivity of current gain to the junction depth can be drastically reduced by a modification in transistor structure. Design criteria for making this structural change are presented as well as the results on actual devices.     

A bipolar lock-layer transistor

A bipolar transistor and a junction field effect transistor are integrated into a “merged” cascode configuration. Viewed as a modified bipolar transistor, this device has a new and favorable combination of common-emitter breakdown voltage and current gain, and is largely free of the Early effect.     

Factors limiting current gain in power transistors

The combined effect of sidewall injection, bandgap narrowing, and Shockley-Hall-Read and Auger recombination in determining emitter efficiency in n-p-n power transistor structures is demonstrated by utilizing a two-dimensional transistor model. The relative importance of each of these effects is calculated as a function of emitter junction depth, emitter surface doping, and injection level. It is shown that in a practical transistor design the reduction in emitter efficiency due to the increased injection of holes into the emitter, resulting from bandgap narrowing caused by heavy doping, is not dominated by the emitter sidewall. Auger recombination is seen to be especially important when bandgap narrowing is present. Enhanced Auger-type recombination is due both to increased minority carrier injection in the emitter as well as current crowding effects. The predictions of the model are compared with results of the measurement of current gain versus current level characteristics on existing devices.     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

Monte Carlo simulation of real-space transfer transistors: devicephysics and scaling effects

Monte Carlo simulations of the real-space transfer transistor (RSTT) are carried out for various bias conditions. Detailed analysis of the RSTT, especially in the saturation regime, is performed. The mechanism responsible for the saturation of the source current is explained in terms of reverse real-space transfer. The operation of the RSTT is compared with that of the charge injection transistor and it is pointed out that the difference in geometry of these two devices leads to different physical operation. The effect of reducing the device dimensions on the RSTT performance is discussed. A reduction in the collector length is found to improve the transconductance. Transient analysis of the RSTT shows that the device with a smaller collector length would exhibit higher cutoff frequencies. A reduction in the width of the collector drift region is shown to result in an increased peak-to-valley ratio in the heater current which makes the drive more efficient for microwave generation     

PMOS input merged bipolar/sidewall MOS transistors (PBiMOStransistors)

A concept of merging vertical n-p-n bipolar and sidewall PMOS transistors into merged PBiMOS transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy ~1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n^- collector of the n-p-n bipolar and the channel of the sidewall PMOS transistors are similar     

新型I~2L电路的试验研究

为了提高I~2L电路的速度,本文利用新型器件——四极并合晶体管代替pnp管进行电流注入,结果表明,在相同注入极电压下,I~2L电路的速度有较明显提高.同时,仍保持工艺简单、适于集成等优点.     

Essential physics of carrier transport in nanoscale MOSFETs

The device physics of nanoscale MOSFETs is explored by numerical simulations of a model transistor. The physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall devices are examined. The results show that the essential physics of nanoscale MOSFETs can be understood in terms of a conceptually simple scattering model     

Analysis of the enhanced hot-electron injection in split-gatetransistors useful for EEPROM applications

When applying a high voltage to the floating gate of a split-gate transistor, enhanced hot-electron injection is observed that can be used for 5-V compatible EPROM or flash EEPROM device operation. The current collected on the gate is equal to the total electron injection current. Charge-pumping measurements and device simulations are used to analyze the electron injection and to determine its exact position in the transistor channel. Gate currents only show a weak dependence on both transistor channel lengths. The width of the spacer between both transistor gate has, however, been determined to be an important injection parameter