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1.
A new differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for low voltage and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control can get rid of the restriction that control voltage is unable to cover the full range of power supply voltage in a conventional VCRO. A three-stage VCRO chip working with 1 V power supply voltage is constructed using 0.18 μm 1P6M CMOS process for verifying the efficacy of the proposed differential delay cell. Measured results of the VCRO chip show that a wide range of operation frequency from 4.09 GHz to 479 MHz, a tuning range of 88%, is achieved for the full range of control voltage from 0 to 1 V. The power consumptions of the chip are 13 and 4 mW for oscillation outputs of 4.09 GHz and 479 MHz, respectively. The measured phase noise is −93.3 dBc/Hz at 1 MHz offset from 4.09 GHz center frequency. The core area of the chip is 106 μm×76.2 μm. 相似文献
2.
An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device
parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) employs
two varactors for fine and coarse tuning. By using a CMOS charge pump with output biasing, the dc fine tuning voltage of the
VCO and the loop dynamics of the PLL are well defined and fairly independent of PVT variations. Device noise in the charge
pump and linearity of the phase detector are much improved by a two-transistor charge pump architecture for fine tuning. We
measured a phase noise below −131 dBc/Hz at 10 MHz offset and below −94 dBc/Hz at 10 kHz offset over a tuning range of 1.2 GHz.
An integrated phase error below 0.6° was measured, corresponding to an rms jitter below 160 fs. The chip was produced in a
0.25 μm low-cost SiGe BiCMOS technology, occupies a chip area of 2.25 mm2 and draws 60 mA from a 3 V supply. 相似文献
3.
Joon-Sung Park SangWoo Kim YoungGun Pu Kang-Yoon Lee 《Analog Integrated Circuits and Signal Processing》2011,66(3):441-447
This paper presents wideband, low voltage CMOS LC-VCO with automatic two-step amplitude calibration loop to compensate the
PVT variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are proposed. The power consumption is 2–6 mA from a 1.2 V supply.
The VCO tuning range is 3.4 GHz, from 2.35 to 5.75 GHz. The measured phase noise is −117 dBc/Hz at the 1 MHz offset when the
center frequency is 4.313 GHz. 相似文献
4.
A new differential delay cell with a complementary current control to increase the control voltage range as well as the operation frequency is proposed for low-voltage operation. The new differential delay cell is employed in a four-stage voltage-controlled ring oscillator (VCRO). The VCRO is implemented using 0.18 m 1P6M CMOS process and 1.8 V supply voltage. Measured results show that a wide operation frequency range from 5.36 to 3.03 GHz is achieved for the full range control voltage from 0 to 1.8 V. Measured phase noise is 107 dBc/Hz at 1 MHz offset from the 5.22 GHz centre frequency. 相似文献
5.
A CMOS transconductor for wide tuning range filter application is presented. The linear transconductor is designed based on
the flipped-voltage follower (FVF) circuit and can work in the weak, moderate, and strong inversion regions to maximize the
transconductance tuning range. The transconductance tuning can be achieved by changing the bias current of the active resistor,
and a ratio of 28 is obtained. The transconductor was evaluated by using TSMC 0.18 μm CMOS process, and the total harmonic
distortion (THD) of −56 dB can be obtained by giving a 12 MHz 0.4 Vpp input swing signal. In the design, the maximum power
consumption is 2 mW with the transconductance of 1.1 mS under a 1.8 V supply voltage. 相似文献
6.
A 70∼900 MHz broadband PLL frequency synthesizer is developed for the single conversion DVB-C receiver in a standard 0.25 μm
CMOS technology. The true 3-band VCO with a novel AAC (Auto-Amplitude Control) circuit provides a wideband amplitude stable
output and a reliable startup without degrading the phase noise performance. A 16/17 dual-modulus prescaler with a new logic
structure has increased the speed. The charge pump current is programmable for wide loop stabilization and phase noise optimization.
The measured results show that the locked range of the frequency synthesizer is 70∼900 MHz. The worst phase noise at 1 k/10 k/100 k/1 MHz
offset frequency is ordinal −65/−85/−112/−128 dBc/Hz and the spur at reference frequency is lower than −90 dBc.The frequency
synthesizer chip dissipates only 16.2 mA from a 3.3 V supply. 相似文献
7.
Lionel Geynet Emeric de Foucauld Pierre Vincent Gilles Jacquemod 《Analog Integrated Circuits and Signal Processing》2007,53(1):43-51
In this paper, the design of two VCOs for wireless multi-standard applications is presented. The oscillation frequencies are
5.2 and 3.3 GHz. These circuits have been produced using CMOS/SOI technology, with body voltage to control power consumption
and phase noise performance. A new architecture for multi-standard applications is proposed. Five standards are covered by
these structures: GSM (900 MHz), GPS (1.5 GHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11 a (5.8 GHz). The tuning range
can vary from 2.45 to 5.8 GHz for the first VCO and from 850 MHz to 1.9 GHz for the second by using frequency divider. The
main idea is to use only two MOS varactors to cover the entire frequency span. The first one is needed to get the matched
frequency variation and the second to adjust the oscillation frequency. Such VCOs can be made thanks to CMOS/SOI technology
advantages, high-Q passives and body voltage biasing that allow current change and power dissipation in the VCO core. These
circuits were produced with a view to producing a single VCO covering all these standards. Switched resonators were therefore
studied. At a frequency offset of 100 kHz, the single side band phase noise measurements were −89 and −93 dBc/Hz at 5.2 and
3.6 GHz respectively. 相似文献
8.
Lihong Zhang Xuguang Zhang Ezz El-Masry 《Analog Integrated Circuits and Signal Processing》2008,54(3):229-236
In this paper we present a bulk-driven CMOS triode-based fully balanced operational transconductance amplifier (OTA) and its
application to continuous-time filters. The proposed OTA is linearly tunable with the feature of low distortion and high output
impedance. It can achieve wide input range without compromising large transconductance tuning interval. Using a 0.18 μm n-well
CMOS process, we have implemented a third-order elliptic low-pass filter based on the proposed OTA. Both the simulation and
measurement results are reported. The total harmonic distortion is more than −45 dB for fully differential input signals of
up to 0.8 V peak–peak voltage. A dynamic range of 45 dB is obtained under the OTA noise integrated over 1 MHz. 相似文献
9.
Tien-Yu Lo Cheng-Sheng Kao Chung-Chih Hung 《Analog Integrated Circuits and Signal Processing》2009,58(3):197-204
A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed
based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance
tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented
with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the
cutoff frequency of 10–20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs
under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency
of 20 MHz under a 1.8 V supply voltage. 相似文献
10.
Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL 总被引:1,自引:1,他引:0
Saiyu Ren John Emmert Ray Siferd 《Analog Integrated Circuits and Signal Processing》2011,68(3):285-298
The design details of a low power/wide tuning range phase locked loop (PLL) is presented in 180 nm CMOS together with the
simulated and post fabrication measured performance. The PLL has been specifically designed for applications requiring a wide
tuning range (1.55–2.28 GHz) while maintaining low power consumption (18 mW) and good phase noise (−100.9 dBc/Hz at 1 MHz).
The tuning range represents significant improvement over other reported PLL CMOS implementations. To illustrate the robustness
of the architecture, a 90 nm CMOS design is included with a 5.8–9.45 GHz tuning range (48%), phase noise of −111.7 dBc/Hz,
and power consumption of 18.6 mW. The stand alone voltage controlled oscillator (VCO) and the PLL were fabricated on a single
180 nm die providing a unique opportunity to analyze and measure both the stand alone VCO phase noise performance and the
integrated PLL phase noise performance. The contributions to the PLL phase noise (phase detector, charge pump, VCO, divider,
and reference source) are delineated and both the theoretical and measured PLL phase noise performance is discussed. Design
tradeoffs are included such as effect of loop bandwidth on phase noise contributions. 相似文献
11.
A sub-1 V 1.6 GHz voltage-controlled oscillator (VCO) was designed and fabricated using 0.35 μm CMOS technology. This LC-based
VCO can operate at a supply voltage as low as 0.8 V. A top-biased PMOS, with capacitor connected in parallel, is used in order
to reduce the noise contribution in the oscillated frequency even at low voltage supply. Moreover, an accumulation MOS varactor
is adopted to provide 29% wider tuning frequency range compared with a diode varactor under same full tuning voltage. With
a 0.8 V supply, this 1.6 GHz top-biased A-MOS VCO consumes 9 mW, included output buffer, with a measured phase noise of −109.3 dBc/Hz
@ 600 kHz offset. 相似文献
12.
A low-power, inductorless, UWB CMOS voltage controlled oscillator is designed in 0.18 μm CMOS technology targeting to a UWBFM
transmitter application. The VCO is a Double-Cross-Coupled Multivibrator and generates output frequencies ranging from 1.55 GHz
to 2.4 GHz. A low-power frequency doubler based on a Gilbert cell, which operates in weak inversion, doubles the VCO tuning
range from 3.1 GHz to 4.8 GHz. The proportionality between the oscillation frequency and the bias current is avoided in this
case for the entire achieved tuning range resulting in a low-power design. The selected architecture provides high suppression,
over 45 dB, for the 1st and 3rd harmonics, while enabling high-frequency operation and conversion gain due to the unbalanced structure and the single-ended
output. The proposed VCO draws 4 mA from a 1.8 V supply, it has a phase noise of −76.7 dBc/Hz at 1 MHz offset from the center
frequency, while it exhibits a very high ratio of tuning range (43%) over power consumption equal to 7.76 dB. 相似文献
13.
This paper describes a SOI LDMOS/CMOS/BJT technology that can be used in portable wireless communication applications. This technology allows the complete integration of the front-end circuits with the baseband circuits for low-cost/low-power/high-volume single-chip transceiver implementation. The LDMOS transistors (0.35 μm channel length, 3.8 μm drift length, 4.5 GHz fT and 21 V breakdown voltage), CMOS transistors (1.5 μm channel length, 0.8/-1.2 V threshold voltage), lateral NPN transistor (18 V BVCBO and h FE of 20), and high Q-factor (up to 6.1 at 900 MHz and 7.2 at 1.8 GHz) on-chip inductors are fabricated. A fully-functional high performance integrated power amplifier for 900 MHz wireless transceiver application is also demonstrated 相似文献
14.
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector
(PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time.
During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator
(DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase
the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured
phase noise of −125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply. 相似文献
15.
A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range 总被引:3,自引:0,他引:3
A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency. 相似文献
16.
Vlademir J. S. Oliveira Nobuo Oki 《Analog Integrated Circuits and Signal Processing》2010,65(1):61-66
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier
equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation
in a 0.35 μm AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of
140 MHz. 相似文献
17.
YoungGun Pu AnSoo Park Joon-Sung Park Kang-Yoon Lee 《Analog Integrated Circuits and Signal Processing》2011,68(3):257-268
In this paper, we propose a low-power all digital phase-locked loop with a wide input range, and a high resolution TDC that
uses phase-interpolator and a time amplifier. The resolution of the proposed TDC is improved by using a phase-interpolator
which divides the inverter delay time and the time amplifier which extends the time difference between the reference frequency
and the DCO clock. The phase noise of the proposed ADPLL is improved by using a fine resolution DCO with an active inductor.
In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the
wide tuning range and to operate at a low-power, a three-step coarse tuning scheme is used. In addition, the DCO gain needs
to be calibrated digitally in order to compensate for gain variations. The die area of the ADPLL is 0.8 mm2 using 0.13 μm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the
effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is −120.5 dBc/Hz with a 1 MHz
offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage. 相似文献
18.
Mohamed Al-Azab 《Analog Integrated Circuits and Signal Processing》2010,65(2):335-339
This paper describes a 5.2 GHz voltage-controlled oscillator (VCO) as a key component in RF transceivers. The circuit includes
a complementary cross-coupled MOSFET as a negative conductance, beside a tank circuit which consists of an optimal on-chip
spiral inductor (L), and an accumulation mode MOS varactor (C(V)). A model for phase noise and figure merit is introduced
and verified through simulation in a standard 0.13 μm CMOS process. The VCO core drew a 4.2 mA of current from a 1.2 V power
supply and a phase noise of −98.5 dBc/Hz at 1 MHz offset from the 5.2 GHz carrier was calculated. The whole performance of
the circuit specifically the tuning range was found to be 26%. 相似文献
19.
Design challenges of a 65 nm CMOS stacked folded differential PA structure for mobile communications
Yohann Luque Nathalie Deltimple Eric Kerhervé Didier Belot 《Analog Integrated Circuits and Signal Processing》2011,66(2):155-162
In this paper, a novel phase-locked loop (PLL) architecture with multiple charge pumps, which is used to design a fast-locking
PLL and a low-phase-noise PLL, is proposed. The effective capacitance and resistance of the loop filter in terms of voltage
is scaled up/down according to the locking status by controlling the magnitude and direction of the charge pump current. Two
PLLs, one with a fast-locking characteristic and the other with a low-phase-noise characteristic, are designed and fabricated
in a 0.35-μm CMOS process based on the proposed architecture. The fast-locking PLL has a locking time of less than 6 μs and
a phase noise of −90.45 dBc/Hz at 1 MHz offset. The low-phase-noise PLL has a locking time of 25 μs, a phase noise of −105.37 dBc/Hz
at 1 MHz offset, and a reference spur of −50 dBc. Both PLLs have an 851.2 MHz output frequency. 相似文献
20.
Bonghyuk Park Seungsik Lee Sangsung Choi Songcheol Hong 《Microwave and Wireless Components Letters, IEEE》2008,18(2):133-135
A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply. 相似文献