功率集成电路TID加固环栅器件研究现状综述

总结了标准工艺下功率集成电路中总剂量辐射(TID)加固环栅MOS器件与环栅功率器件的研究现状,归纳了不同结构形态的环栅器件的性能优劣,推荐8字形环栅MOS器件、华夫饼功率器件及回字形LDMOS器件结构用于功率集成电路的TID加固设计。同时,阐述了现有环栅MOS器件等效W/L的建模情况,提出保角变换是环栅MOS器件等效W/L精确建模的重要方法,最后还给出了环栅器件建库的基本流程。     

功率HIC基板及其工艺布局设计研究

基板选用和工艺布局是功率混合集成电路两项重要技术内容。根据基板材料不同，功率基板及其布线工艺主要分为陶瓷基板和金属基板两大类。常规陶瓷基板以96％Al2O3陶瓷为代表，高导热陶瓷基板以BeO、AIN陶瓷为代表。陶瓷功率基板大部分采用厚膜布线工艺，另一种布线方式是DBC布线。绝缘金属基板的种类很多，最常使用的是铝基板，另...     

Cell-based layout techniques supporting gate-level voltage scalingfor low power

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power saving capability of the approach via logic-level power estimation. In this correspondence, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then, we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead     

基于分形理论的三维系统封装微通道布局设计

为了更好地解决大功率三维系统封装(3D-SIP)芯片散热的问题,将分形理论和翅片型微通道相结合,应用于微米级的微通道布局中,形成新型的平行翅片型微通道、交错翅片型微通道、树状翅片型微通道3种布局.在ANSYS的FLOTRAN中建立了相应模型,得到了大功率芯片结温、芯片温差和3D-SIP的热阻,比较了3种微通道布局对大功率3D-SIP散热特性的影响.研究结果表明,相比其他两种微通道布局,树状翅片型微通道布局使3D-SIP的大功率芯片散热效果最好,为大功率3D-SIP的散热设计提供了很好的参考依据.     

数字集成电路物理设计阶段的低功耗技术

通过一个图像处理SoC的设计实例,着重讨论在物理设计阶段降低CMOS功耗的方法.该方法首先调整PAD摆放位置、调整宏单元摆放位置、优化电源规划,得到一个低电压压降版图,间接降低CMOS功耗;接着,通过规划开关活动率文件与设置功耗优化指令,直接降低CMOS功耗.最终实验结果表明此方法使CMOS功耗降低了10.92%.基于该设计流程的图像处理SoC已经通过ATE设备的测试,并且其功耗满足预期目标.     

Cell-based layout techniques supporting gate-level voltage scalingfor low power

Gate-level voltage scaling is an approach that allows different supply voltages for different gates in order to achieve power reduction. Previous research focused on determining the voltage level for each gate and ascertaining the power-saving capability of the approach via logic-level power estimation. In this paper, we present cell-based layout techniques that make the approach feasible. We first propose a new block layout style and a placement strategy to support the voltage scaling with conventional standard cell libraries. Then we propose a new cell layout style with built-in multiple supply rails so that gate-level voltage scaling can be immediately embedded in a typical cell-based design flow. Experimental results show that proposed techniques maintain good power benefit while introducing moderate layout overhead     

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

A 1 Tb/s 3 W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1 GHz and data rate of 1 Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30 mum in a layout area of 1 mm². The total layout area including 16 clock transceivers is 2 mm² in 0.18 mum CMOS and the chip thickness is reduced to 10 mum. Bi-phase modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. Four-phase time division multiple access (TDMA) reduces crosstalk and the bit-error rate (BER) is lower than 10^-13     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

1-V电源65nm GP CMOS工艺下一款十位80MS/s 1.6mW逐次逼近型模数转换器

This paper presents a 10-bit 80-MS/s successive approximation register(SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip(SoC).By using the top-plate-sample switching scheme and a split capacitive array structure,the total capacitance is dramatically reduced which leads to low power and high speed.Since the split structure makes the capacitive array highly sensitive to parasitic capacitance,a three-row layout method is applied to the layout design.To overcome the charge leakage in the nanometer process,a special input stage is proposed in the comparator.As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock,and a tunable clock generator is implemented.The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP(general purpose) CMOS technology.Measurement results show a peak signal-to-noise and distortion ratio(SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit(FOM) of 94.8 fJ/conversion-step.     

一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计

本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。     

一种阵列式版图布局的低温度系数CMOS带隙基准电压源

设计了一款低温度系数的自偏置CMOS带隙基准电压源电路,分析了输出基准电压与关键器件的温度依存关系,实现了低温度系数的电压输出。后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局,以压缩版图面积。基于65 nm/3.3 V CMOS RF器件模型,在Cadence IC设计平台进行原理图和电路版图设计,并对输出参考电压的精度、温度系数、电源抑制比(PSRR)和功耗特性进行了仿真分析和对比。结果表明,在3.3 V电源和27℃室温条件下,输出基准电压的平均值为765.7 mV,功耗为0.75μW;在温度为-55~125℃时,温度系数为6.85×10~(-6)/℃。此外,输出基准电压受电源纹波的影响较小,1 kHz时的PSRR为-65.3 dB。     

航天测量船测控系统结构总体设计

讨论了航天测量船测控系统结构总体设计,包括天线布局、机房布局、供电、照明、接地、电缆的分类及布局、关键结构问题等方面,并给出了解决方案。     

0．18μm直接式数字频率合成器全定制版图设计

文章采用0．18μm混合信号1P6M1．8W3．3VCMOS工艺,介绍了一种高速直接式数字频率合成器的全定制版图设计。该芯片为数模混合信号IC,电路内部时钟频率达到1GHz。版图设计过程中采用了集成无源金属-绝缘体-金属（MIM）结构电容及深N阱技术,使用了合适的版图布局和电源、地线、时钟网络拓扑结构,最后还对芯片各模块作了版图优化设计。芯片测试结果表明芯片功能全部实现、性能良好,版图设计较好地实现了电路功能。     

Chip layout design of a Josephson LSI circuit for examininghigh-speed operability by using a standard cell automatic placement androuting technique

A chip layout design technique for a high-speed Josephson LSI circuit using an automatic placement and routing technique with a standard cell method has been developed. A chip layout design of a Josephson LSI circuit with 1500 gates for examining high-speed operability with a 1 GHz clock frequency has been successfully obtained. Related to high-frequency power on a high-speed Josephson LSI circuit, a dividing method for a circuit and a balancing method for power loads are proposed     

PCB design techniques for lowest-cost EMC compliance .1

Application of good EMC (electromagnetic compatibility) practices to the design of printed circuit boards (PCBs) usually helps to achieve the EMC performance required of equipment and systems at much lower cost than alternative EMC measures at higher levels of integration, such as whole-product shielding. EMC design is a complex topic, but the proven best EMC practices for generalised PCB layout can be fairly simply stated and grouped into five techniques, which interact with each other to give dramatic improvements in EMC performance. This paper discusses the techniques of circuit segregation, interface suppression and the use of ground and power planes     

基于TDA7482数字功放的PCB设计

介绍了以TDA7482数字功放为例的PCB设计原则和技术规范，对电路设计中的抗干扰性给出了具体的方案和措施，分析了布线中的电磁干扰问题，并找到了解决的办法。线路工程师在设计之初运用这些原则和方法能很好地解决布线中出现的问题。     

功率NLDMOS电学安全工作区的版图设计优化

在不调整制备工艺、不增加工艺成本条件下,研究了管芯版图优化对功率n型横向扩散金属氧化物半导体(NLDMOS)电学安全工作区(E-SOA)的影响。通过研究p^+带嵌入方式、p^+图形形状、p^+分布密度、阵列单元栅宽及总栅数、金属引线方式等进行了版图设计优化和流片。管芯传输线脉冲(TLP)E-SOA测试结果表明,优化后的版图使NLDMOS在5 V工作电压下TLP E-SOA提升约30%,金属引线的加宽和叠加使NLDMOS的开态电流提升约7%。带状紧凑型p^+带且双栅极嵌入的优化版图设计能更好地稳定硅衬底电位,抑制寄生三极管的开启,增大E-SOA,提高器件可靠性。因此,版图设计优化对提升功率NLDMOS的性能和可靠性具有实际意义。     

射频电磁场辐射抗扰度系统中的功放选择

功放选择是射频电磁场辐射抗扰度测试系统设计中的重要一环.分析整个系统中各部件工作时的实际损耗,总结出选择功放的方法;通过实例,介绍如何选择与设计要求相符的功放.     

特种车内可见光通信系统光源布局优化

针对特种车内空间狭小、光源布局受限这一问题,对光照度及接收光功率进行了理论分析,对光源阵列位置下光照度及光功率的直射和一次反射的分布模型进行了分析与仿真。在光照度需求的约束条件下,根据光功率分布均匀原则提出了特种车辆内部由5个阵列光源形成中心补偿形布局的优化方案。仿真结果表明,在2 m2 m1.5 m的狭小空间内,运用该光源布局方案可得到平均接收光功率值为-0.5 dBm时的光照度范围为333.74~466.44 lx,均匀光照率为79.5%,可同时满足车内照度与数据通信需求。     

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-μm² high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-μm CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm×7.4 mm (29 mm²)