单粒子四点翻转自恢复加固锁存器设计

为了容忍日益严重的单粒子多点翻转,提出了一种能够容忍单粒子四点翻转的加固锁存器——QNURL(quadruple node upset recovery latch).该锁存器包含40个同构的双输入反相器,形成5×8的阵列结构,构建了多级过滤的容错机制.通过有效地利用双输入反相器的单粒子过滤特性,当任意4个内部状态节点...     

超大规模集成电路内部单粒子翻转效应仿真

针对超大规模集成电路特征尺寸的逐渐减小,对空间辐射环境越加敏感,从而引发了单粒子翻转效应,造成程序运行出现错误的问题,研究超大规模集成电路内部单粒子翻转效应,并提出抗辐射加固策略.研究以仿真的形式进行,首先对单粒子翻转效应物理机制进行了分析,为后续研究提供指导方向,然后选择被测器件,搭建效应测试平台,设置测试条件以及阐述单粒子翻转效应仿真测试方法.结果表明:脉冲激光的能量越大,单粒子翻转概率越高;只有激光光束照射到超大规模集成电路芯片有源区时,才可获得最低和最大的翻转截面;激光脉冲注量对单粒子翻转截面测试有影响;存储数据和测试模式对单粒子翻转效应测试都无影响.     

Virtex-5系列SRAM型FPGA单粒子效应重离子辐照试验技术研究

针对SRAM型FPGA在空间辐射环境下易发生单粒子效应,影响星载设备正常工作甚至导致功能中断的问题,开展了SRAM型FPGA单粒子效应地面辐照试验方法研究,提出了配置寄存器和BRAM的单粒子翻转效应测试方法,并以Xilinx公司工业级Virtex-5系列SRAM型FPGA为测试对象,设计了单粒子效应测试系统,开展了重离子辐照试验,获取了配置寄存器、BRAM以及典型用户电路三模冗余前与三模冗余后的单粒子翻转效应试验数据和器件单粒子闩锁试验数据,最后利用在轨预示分析软件针对高轨环境进行了在轨翻转率分析计算,可为该器件的空间应用辐射敏感性分析提供基础数据与加固设计指导。     

一种数字电路单粒子翻转测试方法

为提高航天器系统设计的可靠性，避免单粒子效应对航天器系统造成损坏，在单粒子翻转经典测试方法"黄金芯片比较法"的基础上，设计一种硬件实现的测试方法。方法通过对输出高低电平相关区域的重新取舍，采用合适芯片从硬件上实现数据选择器、锁存器与数值比较器的功能优化，并进行FPGA移植，以解决经典方法在电平翻转时出现误判的问题。同时也详细阐述了移植FPGA过程中的器件选取与程序设计。实际测试表明，改进后的测试方法获得了良好的抗干扰性，为单粒子效应模拟试验提供有效的支持。     

抗辐射集成电路单粒子激光试验与仿真分析

使用脉冲激光模拟单粒子效应技术,对抗辐射集成电路进行激光实验,找到抗辐射集成电路版图上的引起单粒子翻转的敏感位置。通过抗辐射集成电路版图与逻辑图对照和对抗辐射集成电路逻辑功能分析,在抗辐射集成电路逻辑功能框图中找到引起单粒子翻转的逻辑功能块,分析该逻辑功能块中信号的属性、信号传输的方向、信号强弱、信号对单粒子敏感程度,最终找到在脉冲激光模拟单粒子试验中出现逻辑功能错误的MOS器件。使用仿真软件模拟辐照试验中的单粒子干扰,对发生逻辑功能错误的MOS器件进行仿真,通过调整MOS器件的宽长比属性和仿真激励模型,找到逻辑功能错误的MOS器件的属性与发生单粒子翻转现象之间的联系,最终找到解决该集成电路单粒子翻转问题的方案并验证成功。     

抗单粒子翻转的加固方法

集成电路受空间粒子辐射容易产生软故障.通过三模冗余、时间冗余和错误检测与纠正等电路结构设计加固方法可对其进行改善,有效增强其抗单粒子翻转的性能,有效防止因辐射产生的软故障.     

一种数字电路单粒子翻转试验系统设计

随着航空航天事业高速发展,抗辐射元器件的使用需求日益旺盛,作为抗辐射性能评估方法之一的单粒子翻转试验愈发体现出重要性。针对单粒子翻转试验条件的设定与优化,设计一种单粒子翻转试验系统。系统可适应绝大部分数字电路的试验需求,采用ARM与FPGA相结合的方式,使用独立设计的DB50分线装置,具备多路输入、多路输出、多路比较的功能。该试验系统驱动能力强、稳定性高,可更有效地进行各类数字电路单粒子翻转效应测试,有助于提高研究效率并缩短开发周期。     

双立互锁单元单粒子效应加固方法研究

经典双立互锁单元主从型触发器存在由逆向驱动引起的单粒子翻转情况。为此,通过在主从两级之间插入缓冲器阻断反向驱动路径来解决该问题。对一款双立互锁加固芯片进行地面重粒子实验,实验结果显示,改进型双立互锁单元触发器不仅能消除单粒子功能中断,而且能减少单粒子翻转情况。     

基于双核锁步的多核处理器SEU加固方法

以单粒子翻转为代表的软错误是制约COTS器件空间应用的主要因素之一;为了满足空间应用对高集成卫星电子系统抗辐照防护的要求,提出了一种面向通用多核处理器的单粒子翻转加固方法,通过软件层面双核互检,在不额外增加硬件开销的前提下,充分提高了COTS器件的可靠性,具有良好的可移植性和较强的工程实用价值;进行软件故障注入实验,在程序执行的关键节点注入错误信息,验证该双核互检方法实用性;实验结果表明双核互锁方法可以100%检测出系统中产生的单粒子翻转,抗软错误能力满足应用需要。     

一种抗单粒子翻转的D触发器

以互锁存储单元(DICE)结构为基础,采用0.35μm CMOS工艺,设计了一种具有抗单粒子翻转的带置位端的D触发器。通过将数据存放在不同节点以及电路的恢复机制,使单个存储节点具有抗单粒子翻转的能力。通过Spectre仿真,测试了触发器的抗单粒子翻转能力。在版图设计中采用增大敏感节点距离和MOS管尺寸的方法进一步提高了D触发器抗单粒子翻转的能力。     

一种交叉互联的高可靠锁存器

现阶段随着CMOS工艺特征尺寸的减小,电路中可能会发生单粒子翻转（Single Event Upset,SEU）的敏感节点之间的距离在不断减小,发生一颗高能粒子引起多个节点同时发生翻转的事件概率正逐渐上升。为了提高电路的可靠性,基于抗辐射加固设计方法,提出了一种能够容忍两个节点同时发生翻转的锁存器。该锁存器以双输入反相器(Double-input Inverter,DI )单元作为核心器件,并且在 DI 单元之间采用了交叉互联的连接方式,减少了器件个数的使用。与传统的具有容错能力的锁存器相比,所提出的结构不仅具有良好的抗双点翻转能力,而且在功耗、延迟以及功耗延迟积（Power Delay Product,PDP）方面都有很大的优势。该结构可靠性高、性能优良,在提高芯片的可靠性方面具有重要意义,有实用价值。     

基于门控时钟的寄存器传输级功耗优化

随着深亚微米技术的发展,功耗已经成为现代超大规模集成电路设计中的一个主要设计约束.本文在设计多点控制协议MPCP模块中,采用插入门控时钟这一技术以降低芯片功耗.针对插入门控寄存器造成测试很难控制这个问题,采取在锁存器的前后加入控制点的方法,解决了由于插入门控时钟而对可测性造成的影响.最后,使用SMIC的0.25um CMOS工艺,并用Synopsys的power complier进行功耗优化,达到了很好的效果.     

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme (DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating scheme in the pulse generation stage. This scheme conditionally disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals and internal nodes of the latch are all eliminated, leading to low power efficiency. Based on SMIC 65 nm technology, extensive post-layout simulation results show that the proposed DIFF-CGS gains an improvement of 41.39% to 56.21% in terms of power consumption, compared with its counterparts at 10% data-switching activity. Also, full-swing operations in both implicit pulse generation and the static latch improve the robustness of the design. Thus, DIFF-CGS is suitable for low-power applications in very-large-scale integration (VLSI) designs with low data-switching activities.     

自适应一致表决算法

容错技术已经在许多领域的高可靠控制中得到应用,N版本程序技术是实现容错的基本手段之一。在软件系统中,表决算法可以屏蔽错误的输出结果。冗余技术可以防止错误的结果传递到系统的下一个子模块中,并且提高系统的安全性。许多表决算法在容错技术中得到广泛的应用,其中一致性表决算法同样得到了广泛的应用。但一致表决算法适合输出结果空间基数小的情况,因此更容易产生相同并错误的结果(IAW)。针对这个问题,提出一种自适应的一致性表决算法,它将版本历史记录信息应用到一致性表决中,降低了不正确结果通过表决的概率,提高了系统安全性和可靠性。实验证明了所提算法的有效性。     

一种高速高分辨率CMOS比较器

本文讨论了一种高速CMOS比较器,采用前置放大器、锁存器和输出驱动级联的结构,通过优化传输速度、增益和失调电压,采用SMIC0.25umCMOS工艺,用CadenceSpectre模拟器仿真,结果表明最小分辨率为1mV,工作频率达到50MHz,功耗2mW。     

Comparative Analysis of the Design Techniques for Low Leakage SRAMs at 32nm

This paper presents a comprehensive overview of leakage reduction techniques prevailing in Static Random Access Memories (SRAMs) by classifying them in three categories namely latch, bitline and read port. The performance of the techniques are evaluated in terms of leakage reduction capability along with the impact on read performance and hold stability through extensive simulative investigations at 32 nm technology node by taking conventional SRAM cell as reference. Further, as SRAMs are susceptible to inter-die as well as intra-die process variations, the performance at different PVT corners is also captured to demonstrate the efficacy of each technique under PVT variations. It is found that among the techniques used for reducing latch leakages, Multi-threshold CMOS technique possess the highest leakage reduction capabilities followed by Drowsy mode and Substrate-bias techniques. The results also indicate that Negative word line technique is more effective at low supply voltages whereas the Leakage biased bitline technique is more effective at high supply voltages for reducing bitline leakages. Amongst the read port leakage reduction techniques, Stack-effect and Dynamic control of power supply rail techniques are capable of suppressing the leakages at high voltages whereas Virtual cell ground technique is more efficacious at low voltages. The impact of technology scaling on SRAM cell performance with leakage reduction techniques is also studied. For the sake of completeness, suggestions are put forward for adopting a particular technique to address leakages at latch, bitline and read port levels.     

Low power noise immune node voltage comparison keeper design for high speed architectures

The demand for high speed and area minimization has directed the designers towards dynamic CMOS logic design. The domino logic is one of the famous logic in dynamic CMOS logic. The designer needs to compromise the circuit speed and power consumption to reduce the impact of noise in domino logic circuit design. In this work, low power domino logic circuit is proposed to decrease power consumption with improvement in noise immunity. The low power consumption is achieved at the cost small sacrifice in delay. However, the proposed logic circuit has attained better Power Delay Product (PDP) as compared to existing noise tolerant circuits. The experimental simulation results shows the proposed logic exhibit 3.4% power reduction when compared with the low power domino logic circuit [10] for two input OR gates. The proposed logic had a little compromise with delay in the existing logics. However, the Power Delay Product (PDP) of proposed logic circuit has reduced as compared to existing techniques. The proposed logic also provides the better improvement in noise immunity parameters such as UNG and ANTE as compared to the existing logics. The proposed logic circuit based application circuit such as 4:1 multiplexer also provides better improvement in case of power consumption and noise immunity.     

GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology

The Carry Select Adder (CSLA) is one of the fastest multi-bit adder architectures being used in various high speed processors. The CSLA is fast but compromises on the area and power consumption due to its complex architecture when implemented using standard CMOS logic. In this work, an alternate implementation of the CSLA architecture is done using Gate Diffusion Input (GDI) logic; instead of the CMOS logic. This approach simplifies the overall architectural dimensions due to reduction in transistor count as well as the power consumption. In this work, various types of CSLA architectures are implemented using the GDI logic and compared with their CMOS logic counterparts in terms of average power, delay and transistor count in 45 nm technology node. The comparative analysis clearly shows that GDI based circuits are better compared to CMOS logic implementations.     

Low power high-speed multithreshold voltage CMOS bus architectures

Low power, high-speed bus architectures, based on low swing voltage technique, using multithreshold voltage transistors are proposed in this paper. Three different classes of driver/repeater/receiver circuits are introduced. The driver circuits are comprised of high threshold voltage MOSFET transistors, in order to reduce their output swing level voltage. For re-pulling up the low swing voltage to full swing, innovated high-speed, cross-coupled latch, voltage receiver circuits are used. In applications having high load capacitance due to long interconnections, novel repeater circuits based also on multithreshold voltage technology are introduced. Using 0.5 μm multithreshold voltage process technology and 1 V supply voltage, SPICE measurements showed up to 45% improvement in the power delay product.