Improved electrical characteristics of CoSi2 usingHF-vapor pretreatment

We have developed a simple process to form epitaxial CoSi₂ for shallow junctions. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF treatment drastically improves the native oxide-induced surface roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM). Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results     

Field emission characteristics of CoSi2/TaN-coatedsilicon emitter tips

This work has improved the emission characteristics of Si emitter tips by coating a CoSi₂/TaN bilayer on the tips. The CoSi₂ layer was grown in situ by a reactive chemical-vapor deposition of cyclopentadienyl dicarbonyl cobalt at 650°C. The TaN was then deposited on the CoSi₂ layer at 550°C by a reactive sputtering of Ta with N as a reactive gas. The CoSi₂/TaN-coated emitters showed a lower turn-on voltage and higher emission current than the CoSi₂- or TaN-coated emitters due to the low work function by TaN and the easy transport of electron by CoSi₂ with low resistivity. The long-term emission stability of CoSi₂/TaN-coated Si emitter was as good as TaN-coated emitter     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

CoSi2 ohmic contacts to n-type 6H---SiC

Cobalt disilicide (CoSi₂) ohmic contacts possessing low specific contact resistivity (_c < 3.0 ± 0.4 × 10⁻⁵ ωcm²) to n-type 6H---SiC are reported. The contacts were fabricated via sequential electron-beam evaporation of Co and Si layers followed by a two-step vacuum anealing process at 500 and 900°C. Stochiometry of the contact so formed was confirmed by Rutherford backscattering spectrometry and X-ray diffraction. Specific contact resistivities were obtained via current-voltage (I-V) analysis at temperatures ranging from 25 to 500°C. _c is compared as a function of carrier concentration, current density, temperature and time at elevated temperature.     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

The influence of Ti capping layers on CoSi2 formation

Cobalt silicide formation is very sensitive to the presence of oxygen. Oxygen contamination may originate from different sources: impurities in the annealing ambient, oxygen incorporated within the deposited Co layer and interfacial oxide at the Co/Si interface. In this work, it is shown that the cause of the sensitivity towards oxygen contamination is the formation of a SiO_x diffusion barrier between CoSi and the unreacted Co. This causes an increase in the activation energy for CoSi formation. Furthermore, we will show that a titanium capping layer eliminates the sensitivity of CoSi₂ formation for oxygen contamination, thus improving the formation of CoSi₂ layers.     

Theoretical and measured characteristics of metal(CoSi2)-insulator(CaF2) resonant tunnelingtransistors and the influence of parasitic elements

We report on the theoretical and measured characteristics of triple-barrier metal (CoSi₂)-insulator(CaF₂) (M-I) resonant tunneling transistors (RTT) grown on an n-Si(111) substrate, and the influence of their parasitic elements on the measured characteristics. First, we analyze theoretical characteristics of an M-I RTT, and then show fabrication process and current-voltage (I-V) characteristics obtained at 77 K, in which several degradations are observed: large resonance voltage, low peak-to-valley (P-V) ratios at negative differential resistance (NDR), and reverse base current. Analysis, taking several parasitic elements (e.g., base resistance, substrate resistance and leakage currents connected to the intrinsic transistor) into account, explains observed characteristics well. Finally, we show the first transistor action with large P-V ratios at 300 K, which is achieved by reducing collector-emitter leakage currents     

Improved electrical properties using SrTiO3/Y2O3 bilayer dielectrics for MIM capacitor applications

In this paper, we show that the capacitance–voltage linearity of MIM structures can be enhanced using SrTiO₃ (STO)/Y₂O₃ dielectric bilayers. The C(V) linearity is significantly improved by combining two dielectric materials with opposite permittivity-voltage responses. Three STO/Y₂O₃ stacks with different thicknesses were realized and compared to a 20 nm STO single layer structure. We observed that an increase in the Y₂O₃ thickness leads to an improvement in the voltage linearity, while maintaining an overall capacitance density greater than 10 fF/μm².     

Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

The material CoSi₂ is preferred for the fabrication of buried silicide films between silicon device layer and buried oxide of SOI substrates for BICMOS integrations. Such an application needs excellent quality of the interface between the silicide and the silicon device layer. Using the conventional cobalt salicide process the roughness and waviness of the interface is too large for a device application. In this presentation three technologies to improve the CoSi₂/Si-interface quality were characterized. Using the first technology a very thin single crystalline CoSi₂ film was fabricated on a silicon substrate. This film acts as initial layer to produce thicker single crystalline silicide films. By the second technology an interlayer between cobalt and the silicon substrate was used to mediate an epitaxial CoSi₂ growth. Different types and materials were tested. Using the third technique a sacrificial layer of polycrystalline silicon between cobalt and the silicon substrate was consumed during the silicidation reaction. This method gives the best results with interface roughness values of less than 1 nm. The interface roughness was measured after CoSi₂ removal using AFM. A possible epitaxial growth of the silicide films was investigated with XRD analysis. Cross sectional SEM images were prepared to analyze the interface waviness and the CoSi₂ structure.     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Atomic-layer-deposited Al2O3 and HfO2 on GaN: A comparative study on interfaces and electrical characteristics

Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ films were deposited on n-type GaN using atomic layer deposition (ALD). The interfacial layer of GaON and HfON was observed between HfO₂ and GaN, whereas the absence of an interfacial layer at Al₂O₃/GaN was confirmed using X-ray photoelectron spectroscopy and transmission electron microscopy. The dielectric constants of Al₂O₃, HfO₂, and composite HfO₂/Al₂O₃ calculated from the C-V measurement are 9, 16.5, and 13.8, respectively. The Al₂O₃ employed as a template in the composite structure has suppressed the interfacial layer formation during the subsequent ALD-HfO₂ and effectively reduced the gate leakage current. While the dielectric constant of the composite HfO₂/Al₂O₃ film is lower than that of HfO₂, the composite structure provides sharp oxide/GaN interface without interfacial layer, leading to better electrical properties.     

Microstructure and electrical characteristics of Ba0.65Sr0.35TiO3 thin films etched in CF4/Ar/O2 plasma

Radio frequency magnetron sputtered Ba_0.65Sr_0.35TiO₃ (BST) thin films were etched in CF₄/Ar/O₂ plasma by magnetically enhanced reactive ion etching technique. The etching characteristics of BST films were characterized in terms of microstructure and electrical properties. Atomic force microscopy and X-ray diffraction results indicate that the microstructure of the etched BST film is degraded because of the rugged surface and lowered intensities of BST (1 0 0), (1 1 0), (1 1 1) and (2 0 0) peaks compared to the unetched counterparts. Dielectric constant and dielectric dissipation of the unetched, etched and postannealed-after-etched BST film capacitors are 419, 346, 371, 0.018, 0.039 and 0.031 at 100 kHz, respectively. The corresponding dielectric tunability, figure of merit and remnant polarization are 19.57%, 11.56%, 17.25%, 10.87, 2.96, 5.56, 3.62 μC/cm², 2.32 and 2.81 μC/cm² at 25 V, respectively. The leakage current density of 1.75 × 10⁻⁴ A/cm² at 15 V for the etched BST capacitor is over two orders of magnitude higher than 1.28 × 10⁻⁶ A/cm² for the unetched capacitor, while leakage current density of the postannealed-after-etched capacitor decreases slightly. It means that the electrical properties of the etched BST film are deteriorated due to the CF₄/Ar/O₂ plasma-induced damage. Furthermore, the damage is alleviated, and the degraded microstructure and electrical properties are partially recovered after the etched BST film is postannealed at 923 K for 20 min under a flowing O₂ ambience.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Study on electrical characteristics and reliability of fluorinated HfO2 for HKMG

The dielectric properties and reliability of fluorinated HfO₂ have been studied. The fluorinated HfO₂ dielectric treated by NF₃ plasma showed improved dielectric characteristics but resulted in interfacial layer (IL) regrowth during the fluorine plasma treatment process, which led to an oxide capacitance reduction and poor electrical characteristics. Through the analysis of chemical composition and electrical characteristics, it has been revealed that the Hf-O bonds in HfO₂ layer were converted to Hf-F bonds by the plasma treatment and then the dissociated oxygen diffused to the IL. In order to suppress the IL regrowth, newly fluorinated HfO₂ has been developed. Reliability of fluorinated HfO₂ dielectric was sharply improved without a decrease in the oxide capacitance at fluorine plasma treatment conditions of low power and temperature.     

Time-dependent-dielectric-breakdown characteristics of Hf-doped Ta2O5/SiO2 stack

The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta₂O₅ films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta₂O₅ were compared. The doped Ta₂O₅ exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta₂O₅ modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.     

Thin films of CoSi2 on Si1−yCy substrate layers

The reaction of Co with epitaxial Si_1−yC_y(001) films is investigated with regard to dependence on annealing temperature and C concentration y. Resistance measurements and RBS analysis reveal a small increase in the disilicide formation temperature. The electrical properties are very similar for thin CoSi₂ films grown at 650°C on Si_0.999C_0.001 and on Si. Whereas the CoSi₂ is fully polycrystalline on Si(001), partially oriented CoSi₂ has been observed on C-containing substrate layers. An increase of the number of epitaxially grown CoSi₂ crystallites has been observed with increasing C concentration.     

Effect of arsenic implantation on electrical characteristics ofLPCVD WSi2/n-Si Schottky contacts

Electrical characteristics of As-implanted low-pressure chemical vapor deposition (LPCVD) WSi₂/n-Si Schottky barriers are reported. It is shown that As implantation results in a significant Schottky-barrier lowering and an increase in the diode ideality factor n. Silicide annealing prior to As implantation is more effective in reducing Schottky-barrier height. Nearly ohmic characteristics were obtained for As-implanted LPCVD WSi₂ Schottky barriers. Arsenic implanted into high-temperature annealed silicide films was more effective in reducing the effective Schottky-barrier height. Detailed SIMS analysis indicated higher As concentration at the silicide/silicon interface when implanted into high-temperature-annealed silicide films     

氮气或氧气气氛退火的氧化铪材料电荷泄漏情况研究

本文中, 使用开尔文探针显微镜,研究了不同退火气氛(氧气或氮气)情况下氧化铪材料的电子和空穴的电荷保持特性。与氮气退火器件相比,氧气退火可以使保持性能变好。横向扩散和纵向泄露在电荷泄露机制中都起了重要的作用。 并且,保持性能的改善与陷阱能级深度有关。氮气和氧气退火情况下,氧化铪存储结构的的电子分别为0.44 eV, 0.49 eV,空穴能级分别为0.34 eV, 0.36 eV。 最后得到,不同退火气氛存储器件的电学性能也与KFM结果一致。对于氧化铪作为存储层的存储器件而言,对存储特性的定性和定量分析,陷阱能级,还有泄漏机制研究是十分有意义的。     

Raman investigation of lattice defects in the CoSi2 synthesis using focused ion beam implantation

CoSi₂ layers were produced by 70 keV Co focused ion implantation into Si(111). Within a comparative study the CoSi₂ layer quality and implantation damage were investigated as a function of pixel dwell-time and substrate temperature. Irradiation damage measurements were done by micro-Raman analysis. The results suggest that the dwell-time dependence of the CoSi₂ layer formation — continuous layers for short and disrupted ones for long dwell-times — is caused by an accordant transition from crystalline to amorphous silicon.