基于线性插值的DDFS中的相位-幅度映射研究

提出了采用线性插值的方法来实现直接数字频率合成器（DDFS）结构中相位到正弦曲线幅度之间的映射（简称“相幅映射”）。该方法使用具有分段连续性质的线性分段来近似正弦函数曲线的第一象限部分；然后根据正弦曲线的象限对称性，重构完整的正弦曲线。文中分析了基于线性插值技术的DDS的频谱特性；然后对基于该方法的DDS的“无杂散动态范围”进行了研究。最后，提出了线性插值系数选择的详细、系统的步骤，从而取得期望的SFDR。     

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.     

Correlated Noise: How it Breaks NMF,and What to Do About it

A novel direct digital frequency synthesizer (DDFS) based on a parabolic polynomial with an offset is proposed in this paper. A 16-segment parabolic polynomial interpolation is adopted to replace the traditional ROM-based phase-to-amplitude conversion methods. Besides, the proposed parabolic polynomial interpolation is realized in a multiplier-less structure such that the speed can be significantly improved. This work is manufactured by a standard 0.13 μm CMOS cell-based technology. The maximum clock rate is 161 MHz, the core area is 0.33 mm², and the spurious free dynamic range (SDRF) is 117 dBc by physical measurements on silicon.     

一种新的正交直接数字频率合成器设计方案

为了提高正交直接频率合成器输出频谱纯度和降低逻辑单元占用率,提出了一种新的分解二阶多项式近似算法。这种算法是将正(余)弦函数分解为几个相关函数,进行二阶多项式近似。与传统二阶多项式近似算法相比,该算法输出频谱纯度较高,无杂散动态范围(SFDR)可达到99.3dBc;该算法所占用的逻辑单元比二阶多项式近似算法减少20%。实验表明,在设计高频谱性能的正交直接数字频率合成器(Quadrature-DDFS)方面,该算法具有明显优势。     

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current source in a thermometer decoded non-linear DAC to allow non-linear interpolation between the conventional, phase limited output levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than −60 dBc and suitable for use in a wide range of instrumentation systems.     

一种基于最佳平方逼近算法的数字频率综合器

提出一种基于最佳平方逼近算法的数字频率综合器的设计方法,同时采用非均匀分段纠正误差方式对输出正余弦波形进行优化。通过MATLAB系统仿真分析结果表明,采用这种新方法设计的数字频率综合器性能具有精度高、误差小和结构简单的优点,最差情况下的无杂散动态范围(SFDR)小于-80dBc。     

一种基于非均匀分段线性插值的直接数字频率合成器

提出了一种基于非均匀分段线性插值的直接数字频率合成器（DDFS）的设计方法．在所设计的DDFS的相位幅度转换模块中．通过对正弦函数的0到π/2段进行非均匀分段,然后在每一段中采用线性插值近似实现．采用此方法。在八分段、十四分段情况下DDFS的无杂散动态范围（SFDR）值分别达到64．7dB、73．3dB。     

Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.     

A 12-Bit Nonlinear DAC for Direct Digital Frequency Synthesis

A 12-bit nonlinear digital-to-analog converter (DAC) was fabricated in a 0.35-$mu$m SOI CMOS process. The nonlinear DAC can implement a piecewise-linear approximation to a sine function and results in significant reduction of complexity and power dissipation when used in direct digital frequency synthesizers (DDFSs). The DDFS look-up table only needs to store offset and gain values for each segment. The look-up table size can be reduced from 11K bits to 544 bits for a 12-bit DDFS with 72 dB spurious-free dynamic range (SFDR). The nonlinear DAC consists of a 12-bit binary-weighted offset DAC and a multiplying DAC. The DACs use a current steering architecture for high-speed operation and the 5 most significant bits of the offset DAC are unary encoded to reduce glitches. The multiplying DAC consists of binary-weighted current sources switched by the partial products of the inputs. Test results show that the DAC has 12-bit accuracy after digital trimming, operates up to 600 MS/s and provides differential outputs of 0.5 V into 50 $Omega$ loads. The SFDR is over 60 dBc below 20 MHz with a maximum of 72 dBc. Radiation tests show the nonlinear DAC can tolerate a total ionizing dose of 200 Krad Si.      

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.     

Arbitrary waveform DDFS utilizing Chebyshev polynomials interpolation

A new technique of arbitrary waveform direct digital frequency synthesis (DDFS) is introduced. In this method, one period of the desired periodic waveform is divided into m sections, and each section is approximated by a series of Chebyshev polynomials up to degree d. By expanding the resultant Chebyshev polynomials, a power series of degree d is produced. The coefficients of this power series are obtained by a closed-form direct formula. To reconstruct the desired signal, the coefficients of the approximated power series are placed in a small ROM, which delivers the coefficients to the inputs of a digital system. This digital system contains digital multipliers and adders to simulate the desired polynomial, as well as a phase accumulator for generating the digital time base. The output of this system is a reconstructed signal that is a good approximation of the desired waveform. The accuracy of the output signal depends on the degree of the reconstructing polynomial, the number of subsections, the wordlength of the truncated phase accumulator output, as well as the word length of the DDFS system output. The coefficients are not dependent on the sampling frequency; therefore, the proposed system is ideal for frequency sweeping. The proposed method is adopted to build a traditional DDFS to generate a sinusoidal signal. The tradeoff between the ROM capacity, number of sections, and spectral purity for an infinite output wordlength is also investigated.     

Circuit modelling of 2-AG indirect pathway via astrocyte as a catalyst for synaptic self repair

A 32-bit read-only memory (ROM)-based direct digital frequency synthesizer with a maximum operating frequency of 2 GHz is presented. The proposed ROM-based design is capable of increasing the operation speed of traditional ROM-based DDFS by eliminating the complex control circuits and adopting a novel pseudo differential ROM. With a 14-bit partially segmented DAC based on Q² Random Walk switching scheme, the prototype DDFS produces a minimum spurious-free dynamic range of 46.38 dBc up to Nyquist frequency at the clock frequency of 2 GHz. This 0.13 μm CMOS chip occupies an active area of 0.55 mm² and dissipates 450 mW with a 1.2-V digital supply and 3.3-V analog supply.     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

An ultra-high-speed direct digital synthesizer with nonlinear DAC and wave correction ROM

This paper presents a novel direct digital synthesizer (DDS) architecture combining Nonlinear DAC with a small-sized wave-correction-ROM (WCR), which achieves both high operating speed and accuracy. A 6?GHz 8-bit DDS chip based on the proposed architecture is designed and fabricated in a 60?GHz GaAs HBT technology. The major blocks of the DDS MMIC based on ECL logic includes an 8-bit pipelined accumulator, an 8?×?8?×?3-bit WCR, two combined digital-to-analog converters (DACs) and an analog Gilbert Cell for sine-wave generation, a 3-to-7 thermometer coder, digital logic gates and registers. A method of using a series of RC networks to terminate the clock tree together with a pot-layout simulation scheme is developed to maintain the clock tree signal integrity. The DDS chip is tested using an on-wafer measurement approach. The measured spurious free dynamic range (SFDR) is 33.96 dBc with a 2.367?GHz output using a 6?GHz maximum clock frequency. The measurement also shows an average SFDR of 37.5 dBc and the worst case SFDR of 31.4 dBc (FCW?=?112) within the entire Nyquist band under a 5?GHz clock. The chip occupies 2.4?×?2?mm² of area and consumes a 3.27?W of power from a single ?4.6?V power supply.     

A 14-b direct digital frequency synthesizer with sigma-delta noise shaping

This paper describes a 14-b direct digital frequency synthesizer (DDFS) utilizing a sigma-delta noise shaping technique to reduce spurs arising from phase truncation. A new phase accumulator architecture adopting a second-order sigma-delta modulator is proposed. The sigma-delta noise shaping eliminates periodicity inherent in the phase truncation error. With the proposed phase accumulator, the significant spurs are reduced, and the spectral characteristics of the DDFS are then determined by finite precision of sine-amplitude output. A prototype DDFS IC in 0.25-/spl mu/m CMOS was fabricated on 0.12-mm/sup 2/ die area. The measured spurious-free dynamic range (SFDR) is greater than 110 dB for 16-b phase value and 14-b sine-amplitude output. The fabricated IC consumes 100 mW with a 2.5-V supply, and correctly operates up to 250 MHz.     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

WRAN系统中基于自适应内插的信道估计算法

提出了一种基于自适应复系数内插的信道估计算法,改善了无线区域网络（WRAN）系统对抗动态多径时延的能力。WRAN是第一个采用认知无线电技术改善频谱效率的宽带接入标准,系统在下行链路中采用了正交频分复用（OFDM）调制技术,而信道估计技术对于采用相干解调的OFDM系统十分重要。传统的OFDM信道频域响应（CFR）估计算法通常采用实系数频域内插的方式,在对抗WRAN系统长多径时延信道时,不能有效地工作。该文在研究实系数FIR内插变换域响应的基础上,提出了一种复系数内插算法。为了同时适用于短时延信道,提出了一种低复杂度、自适应匹配信道最大多径时延的算法。通过仿真,验证了该算法能够对抗更大的多径时延,提高信道估计的精度,改善系统误码性能。