Accurate small-signal modeling of HFET's for millimeter-waveapplications

In this paper we discuss the small-signal modeling of HFET's at millimeter-wave frequencies. A new and iterative method is used to extract the parasitic components. This method allows calculation of a π-network to model the heterojunction field-effect transistor (HFET) pads, thus extending the validity of the model to higher frequencies. Formulas are derived to translate this π-network into a transmission line. A new and general cold field-effect transistor (FET) equivalent circuit, including a Schottky series resistance, is used to extract the parasitic resistances and inductances. Finally, a new and compact set of analytical equations for calculation of the intrinsic parameters is presented. The real part of Y₁₂ is accounted for in these equations and its modeling is discussed. The accounting of Re(Y₁₂ ) improves the S-parameter modeling. Model parameters are extracted for an InAlAs/InGaAs/InP HFET from measured S-parameters up to 50 GHz, and the validity of the model is evaluated by comparison with measured data at 75-110 GHz     

Optimal Design of Resonant Gate Driver for Buck Converter Based on a New Analytical Loss Model

In this paper, the advantages of a new resonant driver are verified thoroughly by the analytical analysis, simulation and experimental results. A new accurate analytical loss model of the power metal oxide semiconductor field effect transistor driven by a current-source resonant gate driver is developed. Closed-formed analytical equations are derived to investigate the switching characteristics due to the parasitic inductance. The modeling and simulation results prove that compared to a voltage driver, a current-source resonant driver significantly reduces the propagation impact of the common source inductance during the switching transition at high (>1 MHz) switching frequency, which leads to a significant reduction of the switching transition time and the switching loss. Based on the proposed loss model, a general method to optimize the new resonant driver is proposed and employed in the development of a 12 V synchronous buck voltage regulator (VR) prototype at 1 MHz switching frequency. The level-shift circuit and digital implementation of complex programmable logic device (CPLD) are also presented. The analytical modeling matches the simulation results and experimental results well. Through the optimal design, a significant efficiency improvement is achieved. At 1.5 V output, the resonant driver improves the VR efficiency from 82.7% using a conventional driver to 86.6% at 20 A, and from 76.9% using a conventional driver to 83.6% at 30 A. More importantly, compared with other state of the art VR approaches, the new resonant driver is promising from the standpoints of both performance and cost-effectiveness.     

Precision measurement technique of integrated MOS capacitor mismatching using a simple on-chip circuit

A precision measurement technique of the capacitor mismatchings of integrated circuits has been required, that is insensitive to parasitic capacitors on the chip, stray capacitors in measurement circuits, and external noises. A new ac measurement technique is developed here that uses an on-chip source-follower circuit and a simple algorithm. The source-follower circuit lowers the output impedance and thereby excludes the effects of external noises and stray capacitors in measurement circuits. In the present technique, capacitively divided ac voltage after the bandpass filter is measured in two steps by exchanging the terminals of the serial capacitors using external switches. Capacitor mismatching, defined by the relative capacitance toleranceDelta C/C, is derived as the ratio of the difference between the two measured voltages to their average. This derivation significantly reduces errors arising from parasitic capacitors on the chip, the nonlinearity of the source-follower circuit, and the pulse wave that can give the gate bias voltage of the source-follower transistor. The measurement error is estimated to be, in the worst case, 0.1 percent ofDelta C/C.     

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.     

Design of MOS-gated bipolar transistors with integral antiparalleldiode

This paper discusses the design of a new power switching device with integral antiparallel diode called MOS gated bipolar transistor (MGBT). The upper region of the MGBT device structure is conductivity-modulated by a positive feedback mechanism to give a lower on-state voltage drop as compared to a power MOSFET while having fast switching and fully MOS-gate controlled characteristics. A comprehensive model for the MGBT is developed and simple analytical equations are used to predict the on-state characteristics of the MGBT. The analytical modeling results are in good agreement with experimental results on fabricated 750 V MGBT devices. The experimentally measured characteristics of the integral antiparallel diode in the MGBT are reported for the first time in this paper     

A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies

A monolithic implementation of series connected MOSFETs for high-voltage switching applications is presented. Using a single low-voltage control signal to trigger the bottom MOSFET in the series stack, a voltage division across parasitic and inserted capacitances in the circuit is used to turn on the entire stack of devices. This voltage division both statically and dynamically safeguards the individual MOSFETs over the entire switching period. Because the output voltage is balanced across each device in the stack for the entire switching period, stress to the oxide and hot-carrier degradation are minimized, even in the event of transient over voltages. This circuit, termed the Stacked MOSFET, is ntimes scalable, allowing for the on-die control of voltages that are ntimes the fabrication processes rated operating voltage. The governing equations for this circuit are derived and reliable operation is demonstrated through simulation and experimental implementation in a 0.35-mum SOI CMOS process. The realized prototype is shown to handle 2times the nominal process operating voltage at a switching frequency of 20 MHz with an input-to-output delay of only 5.5 ns     

Devices and circuits for bipolar (V)LSI

It is shown that bipolar circuits can continue to play an important role in high-performance LSI and VLSI circuits, because power supply voltages and logic swings can be minimized independently of dimensions, and because the speed degradation due to on-chip wiring capacitances is less severe than in MOSFET/MESFET types of circuit. General performance improvements (in speed and packing density) of logic gates are obtained by increasing transistor fT, and decreasing parasitic capacitances, series resistances and device areas, by using oxide isolation, self-aligned techniques and polysilicon electrodes. Fast switching diodes (such as Schottky barrier diodes and lateral polydiodes) improve the flexibility of circuit design. Logic circuits (such as I²L, LS, DTL, ISL, STL, ECL, and NTL), which already perform in LSI and VLSI circuits or are realistic proposals for them, are discussed.     

A Practical Switching Loss Model for Buck Voltage Regulators

In this paper, a review of switching loss mechanisms for synchronous buck voltage regulators (VRs) is presented. Following the review, a new simple and accurate analytical switching loss model is proposed for synchronous buck VRs. The model includes the impact of common source inductance and switch parasitic inductances on switching loss. The proposed model uses simple equations to calculate the rise and fall times and piecewise linear approximations of the high-side MOSFET voltage and current waveforms to allow quick and accurate calculation of switching loss in a synchronous buck VR. A simulation program with integrated circuit emphasis (Spice) simulations are used to demonstrate the accuracy of the voltage source driver model operating in a 1-MHz synchronous buck VR at 12-V input, 1.3-V output. Switching loss was estimated with the proposed model and compared to Spice measurements. Experimental results are presented to demonstrate the accuracy of the proposed model.     

AlGaN/GaN HEMT小信号模型参数提取算法

本文采用了新型的22元件AlGaN/GaN HEMT小信号等效电路模型,较传统的模型,增加了栅漏电导Ggdf和栅源电导Ggsf来表征GaN HEMT的栅极泄漏电流。同时针对新型的栅场板、源场板结构器件,提出了一种改进的寄生电容参数提取方法,使之适用于提取非对称器件的小信号模型参数。为验证此模型,获得了S参数的测试结果和模型仿真结果,此二者的吻合度较高,表明新型的22元件小信号模型精确、稳定而且物理意义明确。     

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.     

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

Delay analysis of BiNMOS driver including high current transients

The BiNMOS gate delay analysis including high current transients has been developed. The modeling equations account for the high electric field effect in the nMOS transistor and emitter crowding, base pushout, and base conductivity modulation in the bipolar transistor. In examining the switching transient of a BiNMOS driver, the base pushout mechanism exhibits a detrimental effect on the gate propagation delay. The circuit modeling methodology provides a fast turn-around design evaluation of sensitivity of process and device parameters into circuit performance. Computer simulation of a BiNMOS driver using the present analysis is compared with PISCES device simulation in support of physical reasoning     

A small-signal linear equivalent circuit of HEMTs fabricated onGaAs-on-Si wafers

A new small-signal linear equivalent circuit for high electron mobility transistors (HEMTs) fabricated on GaAs-on-Si wafers, HEMTs-on-Si, has been proposed. The new equivalent circuit describes the microwave characteristics of HEMTs-on-Si much better than the conventional metal-semiconductor field-effect transistor (MESFET) equivalent circuit does. Influences of the pads, the GaAs-Si interface, and the Si substrate on the microwave characteristics are included in the circuit. It also has a great advantage in that it can separately analyze the intrinsic device characteristics and influences of Si substrate and GaAs-Si interface. Analyzes using the new equivalent circuit show that the crucial problem of HEMTs-on-Si is the larger values of the pad capacitances and the drain-source capacitances than those of HEMTs fabricated on GaAs bulk wafers, HEMTs-on-GaAs, and that the substrate resistivity is not an important factor for microwave performances of HEMTs-on-Si. The microwave performance was improved by the reduction of the pad capacitances     

Theoretical and experimental characteristics of the insulated-gatethyristor (IGTH)

A Insulated-Gate Thyristor (IGTH) design consisting of square cells with high density of MOS channels modulating the resistance of the base region of the NPN transistor of the thyristor structure is described. The on-state characteristics of IGTH structures including the effect of the lateral parasitic bipolar transistor are studied with the help of numerical device simulations and are analytically modeled by simple analytical equations. The variation of IGTH characteristics with temperature and electron-irradiation dose is experimentally studied and the behavior is explained with the help of analytical equations. The modeling results were found to be in good agreement with experimental results obtained on many lots of 600 V-1200 V Insulated-Gate Thyristors (IGTH) fabricated with an active area of 1.3 mm²-0.35 cm². The analytical models developed can also be applied to design and predict the characteristics of other MOS-gated thyristor structures     

A 10 Gb/s hybrid-integrated receiver array module using a planarlightwave circuit (PLC) platform including a novel assembly regionstructure

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing     

A compact model for multiterminal bipolar devices used in smartpower applications

Complex technologies merging low-voltage bipolar devices and vertical current-flow power transistor allow more smart functions at low chip cost but pose problems during the design phase because there is no way to predict the influence of the high-voltage transistor over the control components by using standard bipolar junction transistor (BJT) models. In fact the large inductive load usually present in high-voltage power transistors applications forces both negative substrate voltage and spurious currents that can induce positive feedback among parasitic devices, downgrading the performance of a single device and so of the whole circuit. In this work we introduce a model for the five-terminal bipolar devices used in smart power applications. The model accounts for all main static and dynamic parasitic effects and gives results in very good agreement with experimental data on both simple devices and complex integrated circuits currently implemented in commercial products for microprocessor based engine management systems (EMS's)     

Efficient analytical formulation and sensitivity analysis of neuro-space mapping for nonlinear microwave device modeling

A new computer-aided design (CAD) method for automated enhancement of nonlinear device models is presented, advancing the concept of Neuro-space mapping (Neuro-SM). It is a systematic computational method to address the situation where an existing device model cannot fit new device data well. By modifying the current and voltage relationships in the model, Neuro-SM produces a new model exceeding the accuracy limit of the existing model. In this paper, a novel analytical formulation of Neuro-SM is proposed to achieve the same accuracy as the basic formulation of Neuro-SM (known as circuit-based Neuro-SM) with much higher computational efficiency. Through our derivations, the mapping between the existing (coarse) model and the overall Neuro-SM model is analytically achieved for dc, small-signal, and large-signal simulation and sensitivity analysis. The proposed analytical formulation is a significant advance over the circuit-based Neuro-SM, due to the elimination of extra circuit equations needed in the circuit-based formulation. A two-phase training algorithm utilizing gradient optimization is also developed for fast training of the analytical Neuro-SM models. Application examples on modeling heterojunction bipolar transistor (HBT), metal-semiconductor-field-effect transistor (MESFET), and high-electron mobility transmistor (HEMT) devices and the use of Neuro-SM models in harmonic balance simulations demonstrate that the analytical Neuro-SM is an efficient approach for modeling various types of microwave devices. It is useful for systematic and automated update of nonlinear device model library for existing circuit simulators.     

Improved high-frequency response of InGaAsP double-channel buried-heterostructure lasers

Several modifications of the InGaAsP double-channel buried-heterostructure laser diode are described with reduced parasitic capacitances in order to improve the modulation speed of the laser chip. The parasitic capacitances of the various devices are measured and the data are described in terms of an improved microwave circuit model for BH lasers. A modulation bandwidth of more than 3 GHz is experimentally obtained by means of proton isolation of the laser chip outside the active region.