Epitaxial growth of InP nanowires on germanium

The growth of III-V semiconductors on silicon would allow the integration of their superior (opto-)electronic properties with silicon technology. But fundamental issues such as lattice and thermal expansion mismatch and the formation of antiphase domains have prevented the epitaxial integration of III-V with group IV semiconductors. Here we demonstrate the principle of epitaxial growth of III-V nanowires on a group IV substrate. We have grown InP nanowires on germanium substrates by a vapour-liquid-solid method. Although the crystal lattice mismatch is large (3.7%), the as-grown wires are monocrystalline and virtually free of dislocations. X-ray diffraction unambiguously demonstrates the heteroepitaxial growth of the nanowires. In addition, we show that a low-resistance electrical contact can be obtained between the wires and the substrate.     

New nanocrystalline powder substrates for nitrides layer epitaxy

GaN and related III-V nitride materials have been applied for fabrication of electronic and optical devices. The most important factor limiting the mass production of devices based on III-V nitride materials is the high cost of substrates and the elaborate growth techniques. The lack of large, bulk GaN substrates causes that the epitaxial layer of nitrides must be grown on heteroepitaxial substrates. The most widely applied are monocrystalline sapphire, SiC and silicon substrates; but the question of cheap and available substrates for nitrides growth is still open.In this paper, authors present some results of the growth of nitrides layer by the metal-organic vapor-phase epitaxy (MOVPE) technique on new nanocrystalline powder substrates (compressed Al₂O₃+SiC). The influence of substrate composition (the amount of SiC powder) on the properties of the GaN layer are presented. Also the impact of the conditions of epitaxial process on properties of the nitride layers are discussed.     

硅基沉积氮化镓,碳化硅,III –V 族及其合金材料研究进展

硅基沉积氮化镓, 碳化硅, III-V 族及其合金材料是近年来的研究热点. 氮化镓, 碳化硅及其III-V 材料在光电子和电子元件领域有着广泛的应用.例如大功率, 高速器件, 大型激光器, 紫外探测器等等. 尽管硅基片具有低成本, 大的尺寸,和极好的电热导性能等优点, 硅基片仍没有成为氮化镓, 碳化硅及III – V 的主要沉积基片, 其原因在于硅基片与氮化镓, 碳化硅及III-V 材料之间的热膨胀系数和晶格常数之间的失配. 自从1998年, IBM 的课题组用分子外延方法在硅基片上沉积氮化镓, 并且成功地制备了氮化镓激光器之后, 硅基氮化镓的研究开始备受关注. 近年来的研究发现, 使用氧化铝和氮化铝镓作为过渡层. 硅基氮化镓的热应力及与硅基片之间的晶格失配可以明显降低.在 6英寸的(111) 取向的硅基片上用化学气相方法可以成功地沉积超过一个微米厚的无裂纹的单晶氮化镓. 德国的AZZURRO 公司成功地制备硅基片氮化镓的大功率的蓝色激光器. 美国的NITRINEX公司也生产了硅基氮化镓大功率电子元件. 超大功率的硅基氮化镓电子元件仍在研究中. 在2007年, 英国政府设立了一个固体照明器件的研究项目. 主要着手研究6英寸的硅基氮化镓激光器. 另一方面, 在过去的40年, 超大规模硅基CMOS 技术已有了长足的发展, 下一代低功耗高速逻辑电路要求低的驱动电流, 小的活门尺寸低于 30 nm 和快速反应性能. 这就要求器件通道材料具有很高的电子(或空穴)迁移率. III-V 材料, 例如InSb, InAs, 和InGaAs 具有电子迁移率高达 80000 cm2/VS. 它们将是下一代低于 30 nm 硅基CMOS 器件最好的候选材料. 在 2007 年美国DARPA/MTO 设立了一个研究项目来发展硅基 III-V材料器件, 着重于发展高速硅基III-V材料CMOS 器件. 第一届”硅基氮化镓,碳化硅,III-V及其合金材料研究进展 ”国际会议也将于3月 24日-28日在旧金山MRS 2008年初春季会议上召开.     

III-V complementary metal-oxide-semiconductor electronics on silicon substrates

One of the major challenges in further advancement of III-V electronics is to integrate high mobility complementary transistors on the same substrate. The difficulty is due to the large lattice mismatch of the optimal p- and n-type III-V semiconductors. In this work, we employ a two-step epitaxial layer transfer process for the heterogeneous assembly of ultrathin membranes of III-V compound semiconductors on Si/SiO(2) substrates. In this III-V-on-insulator (XOI) concept, ultrathin-body InAs (thickness, 13 nm) and InGaSb (thickness, 7 nm) layers are used for enhancement-mode n- and p- MOSFETs, respectively. The peak effective mobilities of the complementary devices are ～1190 and ～370 cm(2)/(V s) for electrons and holes, respectively, both of which are higher than the state-of-the-art Si MOSFETs. We demonstrate the first proof-of-concept III-V CMOS logic operation by fabricating NOT and NAND gates, highlighting the utility of the XOI platform.     

III-V nanowire growth mechanism: V/III ratio and temperature effects

We have studied the dependence of Au-assisted InAs nanowire (NW) growth on InAs(111)B substrates as a function of substrate temperature and input V/III precursor ratio using organometallic vapor-phase epitaxy. Temperature-dependent growth was observed within certain temperature windows that are highly dependent on input V/III ratios. This dependence was found to be a direct consequence of the drop in NW nucleation and growth rate with increasing V/III ratio at a constant growth temperature due to depletion of indium at the NW growth sites. The growth rate was found to be determined by the local V/III ratio, which is dependent on the input precursor flow rates, growth temperature, and substrate decomposition. These studies advance understanding of the key processes involved in III-V NW growth, support the general validity of the vapor-liquid-solid growth mechanism for III-V NWs, and improve rational control over their growth morphology.     

Nanoscale semiconductor "X" on substrate "Y"--processes, devices, and applications

Recent advancements in the integration of nanoscale, single-crystalline semiconductor 'X' on substrate 'Y' (XoY) for use in transistor and sensor applications are presented. XoY is a generic materials framework for enabling the fabrication of various novel devices, without the constraints of the original growth substrates. Two specific XoY process schemes, along with their associated materials, device and applications are presented. In one example, the layer transfer of ultrathin III-V semiconductors with thicknesses of just a few nanometers on Si substrates is explored for use as energy-efficient electronics, with the fabricated devices exhibiting excellent electrical properties. In the second example, contact printing of nanowire-arrays on thin, bendable substrates for use as artificial electronic-skin is presented. Here, the devices are capable of conformably covering any surface, and providing a real-time, two-dimensional mapping of external stimuli for the realization of smart functional surfaces. This work is an example of the emerging field of "translational nanotechnology" as it bridges basic science of nanomaterials with practical applications.     

Self-Aligned, Extremely High Frequency III-V Metal-Oxide-Semiconductor Field-Effect Transistors on Rigid and Flexible Substrates

This paper reports the radio frequency (RF) performance of InAs nanomembrane transistors on both mechanically rigid and flexible substrates. We have employed a self-aligned device architecture by using a T-shaped gate structure to fabricate high performance InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with channel lengths down to 75 nm. RF measurements reveal that the InAs devices made on a silicon substrate exhibit a cutoff frequency (f(t)) of ～165 GHz, which is one of the best results achieved in III-V MOSFETs on silicon. Similarly, the devices fabricated on a bendable polyimide substrate provide a f(t) of ～105 GHz, representing the best performance achieved for transistors fabricated directly on mechanically flexible substrates. The results demonstrate the potential of III-V-on-insulator platform for extremely high-frequency (EHF) electronics on both conventional silicon and flexible substrates.     

Monte Carlo simulation of III-V material-based MOSFET for high frequency and ultra-low consumption applications

High-mobility III-V heterostructures are emerging and very promising materials likely to fulfil high-speed and low-power specifications for ambient intelligent applications. The main objective of this work is to theoretically explore the potentialities of MOSFET based on III-V materials with low bandgap and high electron mobility. First, the charge control is studied in III-V MOS structures using a Schr?dinger-Poisson solver. Electronic transport in III-V devices is then analyzed using a particle Monte Carlo device simulator. The external access resistances used in the calculations are carefully calibrated on experimental results. The performance of different structures of nanoscale MOS transistor based on III-V materials is evaluated and the quasi-ballistic character of electron transport is compared to that in Si transistors of same gate length.     

Some limits on donor and acceptor concentrations in silicon and III-V compounds

Various ‘clustering’ effects or precipitates are encountered when the limiting solubility of donors or acceptors in silicon or III-V compounds is exceeded, but little information is available about the phases involved or the mechanism of their nucleation. For Group VI donors in III-V compounds and Group V donors in silicon a particularly simple model is suggested based on the formation of a precursor of a 4-sheet layer lattice (SiAs, GaSe). For Group II acceptors in III-V compounds a self-compensation mechanism is suggested which also eventually leads to precipitation as well as lack of acceptor behaviour. The latter for example can lead to n-type Zn-doped GaAs!     

Crystal structure control in Au-free self-seeded InSb wire growth

In this work we demonstrate experimentally the dependence of InSb crystal structure on the ratio of Sb to In atoms at the growth front. Epitaxial InSb wires are grown by a self-seeded particle assisted growth technique on several different III-V substrates. Detailed investigations of growth parameters and post-growth energy dispersive x-ray spectroscopy indicate that the seed particles initially consist of In and incorporate up to 20?at.% Sb during growth. By applying this technique we demonstrate the formation of zinc-blende, 4H and wurtzite structure in the InSb wires (identified by transmission electron microscopy and synchrotron x-ray diffraction), and correlate this sequential change in crystal structure to the increasing Sb/In ratio at the particle-wire interface. The low ionicity of InSb and the large diameter of the wire structures studied in this work are entirely outside the parameters for which polytype formation is predicted by current models of particle seeded wire growth, suggesting that the V/III ratio at the interface determines crystal structure in a manner well beyond current understanding. These results therefore provide important insight into the relationship between the particle composition and the crystal structure, and demonstrate the potential to selectively tune the crystal structure in other III-V compound materials as well.     

Bottom-up photonic crystal lasers

The directed growth of III-V nanopillars is used to demonstrate bottom-up photonic crystal lasers. Simultaneous formation of both the photonic band gap and active gain region is achieved via catalyst-free selective-area metal-organic chemical vapor deposition on masked GaAs substrates. The nanopillars implement a GaAs/InGaAs/GaAs axial double heterostructure for accurate, arbitrary placement of gain within the cavity and lateral InGaP shells to reduce surface recombination. The lasers operate single-mode at room temperature with low threshold peak power density of ～625 W/cm2. Cavity resonance and lasing wavelength is lithographically defined by controlling pillar pitch and diameter to vary from 960 to 989 nm. We envision this bottom-up approach to pillar-based devices as a new platform for photonic systems integration.     

Study and improvement of interfacial properties in a MIS structure based on p-type InP

Indium phosphide is one of the most promising candidates among the available III-V semiconducting compounds for the development of MIS technology. This is based on the availability of InP substrates and the relatively large band gap. Before the deposition of the insulator, the InP surface must be treated and well passivated (Surf Interface Anal 20 (1993) 803; J Appl Phys 67 (1990) 4173). We have shown that a InSb buffer layer can reduce the phosphorus atom migration and the concentration of defects at the interface. We have studied and characterized electrically two series of substrates using p-type InP, the first one with thin and the second with thick insulator films. The results obtained show clearly the reduction of the defects in the thicker structures protected by the InSb buffer layer.     

Structure of sputtered Ni2P films

Crystalline and amorphous nickel phosphide (Ni₂P) films are grown by d.c. magnetron sputtering onto various substrate materials, including silicon, III-V compound semiconductors, glass and metals (copper and aluminum). X-ray diffraction and transmission electron microscopy studies showed that the film structure changes most sensitively with the thermal conductivity of the substrates.     

Formation of high aspect ratio GaAs nanostructures with metal-assisted chemical etching

Periodic high aspect ratio GaAs nanopillars with widths in the range of 500-1000 nm are produced by metal-assisted chemical etching (MacEtch) using n-type (100) GaAs substrates and Au catalyst films patterned with soft lithography. Depending on the etchant concentration and etching temperature, GaAs nanowires with either vertical or undulating sidewalls are formed with an etch rate of 1-2 μm/min. The realization of high aspect ratio III-V nanostructure arrays by wet etching can potentially transform the fabrication of a variety of optoelectronic device structures including distributed Bragg reflector (DBR) and distributed feedback (DFB) semiconductor lasers, where the surface grating is currently fabricated by dry etching.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

Optimisation of the epi-ready semi-insulating GaAs wafer preparation procedure

The surface quality is crucial for growth of epitaxial layers on III-V semiconductor substrates. In this work the procedures of epi-ready semi-insulating (SI) GaAs wafer preparation were developed. The atomic force microscopy (AFM), triple crystal X-ray diffraction (TCD) and X-ray photoelectron spectroscopy (XPS) were used to monitor morphology and composition of substrates with different chemical treatment history. We propose an optimised epi-ready SI GaAs wafer preparation procedure involving NH₄OH:H₂O₂:H₂O/NaOCl:H₂O₂:H₂O etching/polishing.     

Transition from a disordered to a crystalline state in II–VI and III–V films

The initial stages of HgCdTe growth on Al₂O₃, GaAs, CdTe, and KCl substrates have been studied by electron diffraction. HgCdTe films were produced by pulsed laser deposition and isothermal vapor phase epitaxy. InGaAs films were grown by isothermal chloride epitaxy on GaAs substrates. In the initial stages of the growth process, we observed a transition from an amorphous to a textured polycrystalline phase and then to a mosaic single-crystal structure. We have calculated the critical size of crystalline grains below which amorphization occurs in II-VI and III-V compounds. The critical grain size agrees with the grain size of the disordered (amorphous) phase that forms in the initial stage of epitaxy. We have determined some characteristics of the heterostructures: critical film thickness below which pseudomorphic growth is possible without misfit dislocation generation, elastic stress in the epitaxial system, surface density of dangling bonds at dislocations, and the critical island radius above which no interfacial misfit dislocations are generated.     

The impact of III-V semiconductors on microelectromechanicalsystems

This article examines the special features of the III-V semiconductors, such as gallium arsenide and chemically related compounds, which make them an attractive alternative to silicon-based technology in the field of microelectromechanical systems. As in conventional electronic systems, it is not expected that the III-V compounds will become exclusively used in all instances, but rather a substantial niche market-exploiting the special advantages of the compound semiconductors-is likely to be established     

Nanostructuring of ultra-thin HfO2 layers for high-k/III-V device application

We report on the nanopatterning by electron beam lithography (EBL) and reactive ion etching (RIE) in a SF6/Ar+ plasma of ultra-thin HfO2 films deposited on GaAs (001) substrates for gate oxide application in next generation III-V metal-oxide-semiconductor field effect transistors (MOSFETs). Characterization of the HfO2/GaAs nanostructured samples by atomic force microscopy (AFM), high-resolution scanning electron microscopy (HRSEM), energy-dispersive X-ray spectroscopy microanalysis (EDX) and transmission electron microscopy (TEM) has shown the formation of well defined HfO2 patterns with nanometre-scale linewidth control and anisotropic profiles. In addition, atomically smooth, stoichiometric and residue-free bottom GaAs etched lines with a lateral dimension of approximately 50 nm have been demonstrated.     

Nanoscale InGaSb heterostructure membranes on Si substrates for high hole mobility transistors

As of yet, III-V p-type field-effect transistors (p-FETs) on Si have not been reported, due partly to materials and processing challenges, presenting an important bottleneck in the development of complementary III-V electronics. Here, we report the first high-mobility III-V p-FET on Si, enabled by the epitaxial layer transfer of InGaSb heterostructures with nanoscale thicknesses. Importantly, the use of ultrathin (thickness, ~2.5 nm) InAs cladding layers results in drastic performance enhancements arising from (i) surface passivation of the InGaSb channel, (ii) mobility enhancement due to the confinement of holes in InGaSb, and (iii) low-resistance, dopant-free contacts due to the type III band alignment of the heterojunction. The fabricated p-FETs display a peak effective mobility of ~820 cm(2)/(V s) for holes with a subthreshold swing of ~130 mV/decade. The results present an important advance in the field of III-V electronics.