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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(1):21-25
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Young-Won Kim Joo-Seong Kim Jong-Woo Kim Bai-Sun Kong 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(5):437-441
In this paper, a set of CMOS differential logic circuits are introduced for use in low-power application. They perform a conditional operation for statistical power reduction during logic operation. The self-precharged version of the logic family provides additional power saving by allowing the use of a small-swing clock. Synchronous counters and bidirectional shift registers were designed in a 0.18-mum CMOS process technology to assess the performance of the proposed technique. The measurement results indicate that the counter with the proposed logic family achieves 50% power reduction compared with that of the conventional logic family. They also indicate that the shift registers with the proposed technique achieve 44%-63% power reduction at a typical switching activity of 0.25. 相似文献
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We report on the design and characterization of an ultralow-power converter, designed for use in baseband digitization in wireless sensor network radio receivers. The converter uses a successive approximation architecture and operates robustly with a supply voltage as low as 450 mV, overcoming charge leakage limitations. Implemented in a 90 nm CMOS process, this design achieves a figure of merit of 0.14 pJ/Conv.Step for the converter core and shows the integration of a complete data-conversion subsystem, including reference generation, from a 0.5 V supply. 相似文献
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Carbognani F. Buergin F. Felber N. Kaeslin H. Fichtner W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(7):830-836
Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V dd-to-ground paths also contributes to a significant decrease of static consumption. 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2009,56(2):440-452
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A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay 总被引:1,自引:0,他引:1
Tsou S.-C. Li C.-F. Huang P.-C. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(12):1436-1440
This brief presents a new circuit architecture for linear-in-decibel, constant-bandwidth variable gain amplifier (VGA). To obtain high linearity under low-voltage operation, this VGA is a closed-loop structure. In loop amplifier design, two techniques are applied: first, the loop amplifier is given finite input impedance. This arrangement keeps the VGA bandwidth constant under different gain setting. Second, a current-buffered compensation is applied for loop stability. Compared to the Miller compensation, this method achieves wider bandwidth. The prototype chip using 0.18-mum CMOS technology demonstrates that -10- to 20-dB gain and 0.5- to 30-MHz bandwidth can be programmed independently. The group delay difference within 30-dB gain control range is smaller than 1%. The total circuit dissipates 1.35 mA from a 1.8-V supply 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2008,55(7):1884-1896
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《Solid-State Circuits, IEEE Journal of》2008,43(10):2229-2238
This paper reports a fully monolithic subthreshold CMOS receiver with integrated subthreshold quadrature LO chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage boosting, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling have been combined to lower the total power consumption. The subthreshold receiver, consisting of the switched-gain low noise amplifier, the quadrature mixers, and the variable gain amplifiers, consumes only 1.4 mW of power and has a gain of 43 dB and a noise figure of 5 dB. The entire quadrature LO chain, including a stacked quadrature VCO and differential cross-coupled buffers, also operates in the subthreshold region and consumes a total power of 1.2 mW. The subthreshold receiver with integrated LO generation is implemented in a 0.18 mum CMOS process. The receiver has a 3-dB IF bandwidth of 95 MHz. 相似文献
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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(1):11-15
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《Solid-State Circuits, IEEE Journal of》2008,43(11):2492-2502
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Nii K. Yabuuchi M. Tsukamoto Y. Ohbayashi S. Imaoka S. Makino H. Yamagami Y. Ishikura S. Terano T. Oashi T. Hashimoto K. Sebe A. Okazaki S. Satomi K. Akamatsu H. Shinohara H. 《Solid-State Circuits, IEEE Journal of》2008,43(1):180-191
The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the process and temperature variations. For the sake of not only enlarging the write margin but also reducing power consumption and speed overhead, the divided dynamic power-line scheme based on a charge sharing is adopted. Test chips of 512-Kb SRAM macros and isolated memory cell TEGs are fabricated using 45-nm bulk CMOS technology. Two types of 6-T SRAM cells, whose sizes were 0.245 mum2 and 0.327 mum2 were designed and evaluated. From the measurement results, we achieved over 100-mV improvement for static noise margin, and 35 mV for write margin for both SRAM cells at 1.0-V worst condition by using assist circuitry. It enables the wordline level to keep higher voltage at the slowest condition than the typical process condition, which results in 83% improvement of the cell current compared with the conventional assist circuit. Furthermore, the minimum operating voltage in the worst case condition was improved by 170 mV, confirming a high immunity against process and temperature variations with less than 10% area overhead. 相似文献
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A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA 总被引:2,自引:0,他引:2
《Solid-State Circuits, IEEE Journal of》2009,44(8):2126-2137
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Lueftner T. Berthold J. Pacha C. Georgakos G. Sauzon G. Hoemke O. Beshenar J. Mahrla P. Just K. Hober P. Henzler S. Schmitt-Landsiedel D. Yakovleff A. Klein A. Knight R. J. Acharya P. Bonnardot A. Buch S. Sauer M. 《Solid-State Circuits, IEEE Journal of》2007,42(1):134-144
To meet the widely varying speed and power requirements of multifunctional mobile devices, an appropriate combination of technology features, circuit-level low-power techniques, and system architecture is implemented in a GSM/Edge baseband processor with multimedia and mixed-signal extensions. Power reduction techniques and performance requirements are derived from an analysis of relevant use cases and applications. The 44 mm2 baseband processor is fabricated in a 90-nm low-power CMOS technology with triple-well option and dual-gate oxide core devices. The ARM926 core achieves a maximum clock frequency of 380 MHz at 1.4-V supply due to the usage of thin oxide (1.6 nm) devices. Power dissipation can be adapted to the performance requirements by means of combined voltage and frequency scaling to reduce active power consumption in medium-performance mode by 68%. To reduce leakage currents during standby mode, large SRAM blocks, nFET sleep transistors, and circuit components with relaxed performance requirements are implemented using devices with 2.2-nm gate oxide thickness 相似文献
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《Solid-State Circuits, IEEE Journal of》2009,44(4):1216-1226
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This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level. 相似文献
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《Solid-State Circuits, IEEE Journal of》2009,44(11):2901-2910
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Afsahi A. Rael J.J. Behzad A. Hung-Ming Chien Pan M. Au S. Ojo A. Lee C.P. Anand S.B. Chien K. Wu S. Roufoogaran R. Zolfaghari A. Leete J.C. Long Tran Carter K.A. Nariman M. Yeung K.W.-K. Morton W. Gonikberg M. Seth M. Forbes M. Pattin J. Gutierrez L. Ranganathan S. Ning Li Blecker E. Lin J. Kwan T. Zhu R. Chambers M. Rofougaran M. Rofougaran A. Trachewsky J. Van Rooyen P. 《Solid-State Circuits, IEEE Journal of》2008,43(5):1101-1118
A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm2 of area in a digital 0.13 mum CMOS process of which 0.29 mm2 is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end. 相似文献