Computer-aided design of VLSI FIR filters

A CAD tool is presented for producing very high-throughput FIR filters. Because the CAD tool is application-specific, it is a very high-level tool. An engineer only needs to specify 1) the filter order, N; 2) the input word size; and 3) the output word size. Using this information, the CAD tool generates CIF files for a filter system that can process 10N million samples per second. The purpose of the paper is to illustrate the benefits of applying both bit-level systolic array architecture and application-specific CAD to the problem of FIR filtering. The resulting CAD system reduces the costs of very high-throughput FIR filters with respect to design, fabrication, and operation.     

Computer-aided design in VLSI device development

Computer-aided design (CAD) has been used extensively in the development of VLSI MOS technology at Hewlett-Packard Laboratory. The CAD system for MOS device design is described. The development of the p-channel transistor with submicrometer channel length, trench isolation in CMOS, and side-wall-masked isolation (SWAMI) for VLSI technology are then presented, followed by a discussion of the techniques used in the simulation of parasitic capacitances in multilayer interconnects for circuit performance evaluations.     

Computer-aided design for VLSI circuit manufacturability

It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented     

Computer-aided design of electronic circuits a user's viewpoint

Computer-aided analysis of electronic circuits is examined from the standpoint of the user. A general discussion of program requirements is presented, and several numerical and practical aspects of computer-aided electronic circuit design are given. The engineer's role is discussed in terms of the information and insight needed by the user, and some of the methods utilized in developing computer analysis capabilities at a particular laboratory are given. On-line design is reviewed, with particular emphasis on graphical input and output systems. A design supervisory program is described that would render on-line circuit design a practical reality. Finally, the impact of on-line systems upon computer-aided analysis is examined with reference to the time-sharing system, OCTOPUS, at Lawrence Radiation Laboratory, Livermore, Calif.     

Computer-aided design and characterization of digital MOS integrated circuits

A computer-aided circuit-simulation method is developed to enable the design, characterization, and optimization of MOS integrated circuits. The computation of dc and transient characteristics is done in terms of physical device parameters extracted from processing information and incorporated in an analytical device model. It is demonstrated that any MOS circuit configuration (with its associated series resistances and parasitic devices) can be analyzed in terms of an equivalent inverter. Input-output transfer characteristics are obtained by superposition of the load and transistor I-V characteristics, providing the necessary information for dc > `worst-case' design. A simple device model was used to compute circuit transient response. All the computed characteristics are in good agreement with measurements performed on integrated circuits.     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

Towards an automated design flow for memristor based VLSI circuits

As today's CMOS technology is gradually scaling down to its physical limits, emerging technologies are under research as alternatives in the future, such as carbon nanotube, magnetic tunneling junction, memristor. Among them, memristor is a promising candidate to implement the futuristic VLSI circuits. It provides a great scalability, near-zero standby power consumption, etc. In order to design memristor based VLSI circuits and explore their potential, it is crucial to develop an automated design flow. However, such a design flow is still missing so far. This paper proposes an automated design flow, Mosys by reusing parts of existing CMOS VLSI circuit design tools. Mosys provides a circuit design flow from a Verilog programming interface to performance estimation models. In addition, it employs a probabilistic power estimation model instead of one based on exhaustive-searching method. In our experiments, it significantly reduces the running time up to over 3000 times with a marginal error (<1%), as compared to the state-of-the-art. To verify the whole Mosys flow, several integer arithmetic functional units (e.g., add, multiply) are described in Verilog and implemented. In addition, Mosys is compared with the state-of-the-art using the EPFL benchmark suite. The results show that Mosys significantly improves the area (6.29x) and delay (4.68x) on average.     

Computer-aided design for integrated circuits: trying to bridge the gap

CAD performance in the field of simulation, testing, and layout is compared to the increase of digital integrated systems complexity. This complexity already exceeds the fundamental limits of existing software, especially in the testing area. On the other hand, fully manual layout of VLSI leads to unreasonably long design times and extremely high risks. This will favor design automation methods in layout. Testability and layout will most likely impose some sacrifice of VLSI overcapacity to a more structured system architecture. This architecture will lead to testable dedicated VLSI system design through the use of automated design software to keep development costs low.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

Power-supply current diagnosis of VLSI circuits

This paper presents a technique based upon the power supply current signature (PSCS) which allows testing of mixed-signal systems, in situ. The PSCS contains important information concerning the operational status of the system; such information can be extracted using approaches based on statistical signal detection theory. The fault-detection performance of these techniques is superior to that achieved through autoregressive modeling of the PSCS. These methods are suitable for production testing of cost-sensitive devices and field testing of mission-critical systems     

Computer-aided design of large-scale integrated I/SUP 2/L logic circuits

Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, computer simulation of I/SUP 2/L logic circuits, interconnection pattern generation, and preparation of a final layout plan.     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

Computer-aided design

The November issue of the Proceedings of the IEEE will be a special issue on computer-aided design, consisting of many papers on specialized aspects of this growing field. To put the new development in proper perspective, this article examines just what it is that justifies all the excitement. It discusses the nature of the engineering design process, man-computer systems, both passive and active computer graphics, nongraphic applications, and problems of computer technology, and points out for engineers the importance of computer-aided design for the future.     

High-speed parallel CRC circuits in VLSI

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates     

High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Estimating power dissipation in VLSI circuits

With the shift to low power IC design for personal computing and communication applications, designers' priorities turn to accurate and efficient estimation of power consumption in ICs. Traditional current and power estimation techniques based on a SPICE-like simulation do not provide the necessary efficiency for such an application, and thus new approaches have been recently proposed. In this, the first of a series of articles that reflect the new orientation of this column, Professor Farid Najm of the University of Illinois at Urbana-Champaign presents an overview of different techniques for estimating power consumption in large-scale IC designs. He also discusses computer aided design tools to help in the task     

Ground bounce in digital VLSI circuits

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.