新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

硅基螺旋电感的几何参数设计和优化

使用三维电磁场模拟的方法对相同硅衬底结构下不同布图结构的螺旋电感进行了模拟和分析.通过改变电感匝数、电感金属的宽度和间隔以及电感的内径,模拟和分析了电感性能的变化.给出了引起电感性能变化的原因.结果表明优化电感的几何参数可以有效地改善电感性能.得出了一些实用的设计原则,可有效地指导射频集成电路中集成电感的设计.     

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

使用三维电磁场模拟的方法对相同硅衬底结构下不同布图结构的螺旋电感进行了模拟和分析.通过改变电感匝数、电感金属的宽度和间隔以及电感的内径,模拟和分析了电感性能的变化.给出了引起电感性能变化的原因.结果表明优化电感的几何参数可以有效地改善电感性能.得出了一些实用的设计原则,可有效地指导射频集成电路中集成电感的设计.     

Modeling and Layout Optimization of Differential Inductors for Silicon-Based RFIC Applications

A scalable RF differential inductor model has been developed, enabling device performance versus layout size tradeoffs and optimization as well as accurate circuit predictions. Comparing inductors with identical inductance values up to an operating frequency of 10 GHz, large conductor width designs are found to yield good performance for inductors with small inductance values. As differential inductance or operating frequency increases, interactions between metallization resistive and substrate losses discourage the use of large widths as it consumes silicon area and degrades device performance.     

宽带硅衬底RF片上螺旋电感物理模型

针对高损耗硅衬底,源自部分元等效电路方法考虑了趋肤效应和邻近效应对螺旋电感中串联电感L_s、串联电阻R_s频率特性的制约,并基于全耦合变压器模型计入了复杂的衬底涡流损耗,从而建立了一种新的片上螺旋电感物理模型.通过与全波分析方法对比,验证了在20GHz范围内由该模型导出的等效电感L_eff、等效电阻R_eff和Q值误差仅在7%以内.该模型可望用于硅基射频集成电路中电感进一步的理论探讨和优化设计.     

硅基片上螺旋电感宽带物理模型

针对高损耗硅衬底,基于部分元等效电路方法和麦克斯韦电磁场理论,计入了趋肤效应、邻近效应和衬底涡流损耗对螺旋电感串联电感Ls与串联电阻Rs频率特性的制约,并通过n等效电路结构模拟了寄生电容的分布特性,从而建立了一种新的片上螺旋电感物理模型。通过与全波分析方法对比,验证了在20GHz范围内由该模型导出的等效电感Leff,等效电阻Reff和Q值误差均在7%以内。该模型可望用于硅基射频集成电路中螺旋电感进一步的理论探讨和优化设计。     

埋入电容和电感的LTCC低温烧结基板

概述了环境友好的(不含Pb和Cd)的埋入电容和电感用的LTCC低温烧结基板。介质常数为50～250,导磁率为50～100以上,适用于低成本的埋入微型无源元件。     

Investigation of DC and RF Performance of Novel MOSHEMT on Silicon Substrate for Future Submillimetre Wave Applications

Semiconductors - In this work, the DC and RF performance of a 20 nm gate length novel metal oxide semiconductor high electron mobility transistor (MOSHEMT) on Silicon substrate is studied using...     

Temperature Effects on the Performance of On-Chip Spiral Inductors Used in RF(MM)ICs

Based on the measured S-parameters and proposed circuit model for on-chip spiral inductors, the overall effects of temperature rise on the inductor performance are examined in this paper. For circular spiral inductors on silicon substrates, it is shown that when the temperature increases from 25°C to 85°C, the peak values of Q-factor (Q _max) of these inductors, corresponding to the turn number N = 3 to 7, decrease about 8.8% to 19%, respectively. The metal trace and silicon substrate resistances both increase linearly with temperature, while the capacitance of silicon substrate has a negative temperature coefficient. For a square spiral inductor on GaAs substrate, its Q _max decreases about 37.2% as temperature increases from 25°C to 185°C. The corresponding frequency f _max tends to shift from 9.44GHz to 7.73GHz, and it is reduced about 18.1%.     

Dielectric Resonator Antenna on Silicon Substrate for System On-Chip Applications

This paper presents for the first time the design and performance of a novel integrated dielectric resonator antenna fabricated on a high conducting silicon substrate for system on-chip applications. A differential launcher to excite the ${rm TE}_{01delta}$ mode of the high permittivity cylindrical dielectric resonator was fabricated using the IBM SiGeHP5 process. The proposed antenna integrated on a silicon substrate of conductivity 7.41 S/m has an impedance bandwidth of 2725 MHz at 27.78 GHz, while the achieved gain and radiation efficiency are 1 dBi and 45% respectively. The design parameters were optimized employing Ansoft HFSS simulation software. Very good agreement has been observed between simulation and experimental results. The results demonstrate that integration of dielectric resonator antennas on silicon is viable, leading to the fabrication of high efficient RF circuits, ultra miniaturization of ICs and for the possible integration of active devices.      

A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0

A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately plusmn400ppm total frequency accuracy is achieved over process variations, plusmn10% variation in the USB power supply voltage and temperature variation from -10 to +85degC. Measured period and cycle-to-cycle jitter are 6.78 ps_rms and 8.96 ps_rms, respectively. Fabricated in a 0.35 mum CMOS technology, the clock generator occupies 0.22 mm² and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply     

Modeling and Simulation of Spiral Inductors in Wafer Level Packaged RF/Wireless Chips

In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP)RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic)simulations. The performance of spiral inductors fabricated with various geometrical and technological parameterswas analyzed. It is shown that Q (the quality factor) and f _res (theself-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line,which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embeddedcomponents, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Throughthis study, optimal structures for such components are identified and guidelines for design and fabrications arederived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful todetermine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a longtime.     

The CHIP - A Design Guide for Reducing Substrate Noise Coupling in RF Applications

This article discusses a set of design guidelines to reduce the on-chip substrate noise coupling in RF and mixed signal applications. Measurement data is presented to compare the various signal isolation techniques. A design flow is calibrated to the measured data and is used to expand the design guide to include the effects of the geometrical and electrical parameters of the isolation structures as well as the frequency of operation on the isolation level. A set of guidelines is presented to the reader as a summary of the studied experiments     

衬底温度对直接光CVD SiO2薄膜特性的影响

采用以低压氙(Xe)气激发真空紫外光作光源,以SiH4和O2作反应气体的直接光CVD技术淀积SiO2薄膜.通过椭圆偏振法、红外光谱法、C-V特性法对不同衬底温度下淀积的SiO2薄膜的特性进行研究.结果表明: 衬底温度在40～200℃范围内,薄膜的折射率在1.40～1.46之间,在沉积膜的红外光谱中未出现与Si-H、Si-OH相对应的红外吸收峰.SiO2薄膜中固定氧化物电荷密度受衬底温度影响较大,其最小值可达1.73×1010cm-2.     

衬底温度对直接光CVD SiO2薄膜特性的影响

采用以低压氙(Xe)气激发真空紫外光作光源,以SiH4和O2作反应气体的直接光CVD技术淀积SiO2薄膜.通过椭圆偏振法、红外光谱法、C-V特性法对不同衬底温度下淀积的SiO2薄膜的特性进行研究.结果表明: 衬底温度在40～200℃范围内,薄膜的折射率在1.40～1.46之间,在沉积膜的红外光谱中未出现与Si-H、Si-OH相对应的红外吸收峰.SiO2薄膜中固定氧化物电荷密度受衬底温度影响较大,其最小值可达1.73×1010cm-2.     

衬底温度对磁控溅射法制备的ZnO:In薄膜光电性能的影响

以粉末靶为溅射源,采用射频磁控溅射法在玻璃衬底上制备掺铟氧化锌(ZnO:In)透明导电膜.利用X射线衍射仪、原子力显微镜、霍尔测试仪,以及分光光度计等对不同衬底温度下生长的ZnO:In薄膜的结构、光电性能进行表征.结果表明,所有制备的ZnO:In薄膜均为六角纤锌矿结构的多晶膜,具有(002)择优取向.ZnO:In薄膜的电阻率随着衬底温度的升高先减小后增大,当衬底温度为100℃时,薄膜的最低电阻率为3.18×10~(-3)Ω·cm.制备的薄膜可见光范围内透过率均在85%以上.

Abstract：

Indium doped zinc oxide (ZnO : In) films were deposited on glass substrates by RF magnetron sputtering method using a powder target.The influence of the substrate temperature on the structure,optical and electrical properties was investigated by X-ray diffraction (XRD),atom force microscope (AFM),Hall measurement and optical transmission spectroscopy.The results show all the obtained films are polycrystalline with a hexagonal wurtzite structure and grow preferentially in the (002) direction,and the grain size is about 22～29 nm.The conductivity of the ZnO : In films change with the substrate temperature,and the lowest electrical resistivity is about 3.18 × 10~3 Ω·cm for the samples deposited at substrate temperature 100 ℃.The transmittance of our films in the visible range is all higher than 85%.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Ultralow Temperature Processing and Integration of Dielectric Resonators on Silicon Substrates for System-on-Chip Applications

Ultralow temperature processing of Ba₂Ti₉O₂₀ thin-film ceramics and the attachment of a porous dielectric resonator cylinder on a conducting prepatterned silicon substrate have been accomplished using a hydrothermal process at 150degC/3 h. Enhanced densification and mechanical strength at the bulk ceramic-thin-film interface were induced by a dissolution-crystallization process involving a sol-gel solution under 13-15 atm pressure. Recrystallization forms electrical bridges between powder particles to form an interconnected microstructure, which eliminates grain boundary defects and, hence, improves the dielectric properties. This method has potential for growth of dielectric resonators on integrated circuits for system-on-chip applications and is implemented for the fabrication of an integrated dielectric resonator antenna.