基于Kaczmarz迭代的大规模MIMO系统低复杂度软输出信号检测

大规模MIMO系统上行链路中,最小均方误差（MMSE）算法能获得接近最优的线性检测性能,但是涉及复杂度较高的矩阵求逆运算.本文基于Kaczmarz迭代提出一种低复杂度软输出信号检测算法,在算法实现中避免了矩阵求逆运算,将实现复杂度由O（K³）降为O（K²）.同时,引入了最优松弛参数进一步加快算法收敛,最后给出了两种用于信道译码的LLR的近似计算方法.仿真结果表明：所提出的Kaczmarz迭代软输出信号检测算法经过两到三次简单的迭代即可较快地收敛,并达到接近MMSE检测算法的误码率性能的水平,其性能与复杂度均优于基于矩阵近似求逆的一类检测算法.     

Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio

This paper presents a programmable MMSE soft-output MIMO symbol detector that supports 600 Mbps data rate defined in 802.11n. The detector is implemented using a multi-core floating-point processor and configurable soft-bit demapper. Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of channel processing with sufficient numerical stability for large channel matrices. When compared to several existing fixed-functional solutions, the detector proposed in this paper is smaller and faster. More important, it is programmable and configurable so that it can support various MIMO transmission schemes defined by different standards.     

基于迭代并行干扰消除的低复杂度大规模MIMO信号检测算法

基于干扰消除思想该文提出一种适用于大规模MIMO系统上行链路的低复杂度迭代并行干扰消除算法,在算法实现中避免了线性检测算法所需的高复杂度$({\cal O}({K^3}))$矩阵求逆运算,将复杂度保持在$({\cal O}({K^2}))$。在此基础上,引入噪声预测机制,提出一种基于噪声预测的迭代并行干扰消除算法,进一步提高了硬判决检测性能。考虑天线间残留干扰,将干扰消除思想运用到软判决中,最后提出一种基于迭代并行干扰消除的低复杂度软输出信号检测算法。仿真结果表明：提出的信号检测方法的复杂度优于MMSE检测算法,经过几次简单的迭代,算法即快速收敛并获得接近甚至优于MMSE检测算法的误码率性能。     

基于并行计算的数字信号处理器

针对传统信号处理系统不能为日益复杂的无线通信系统提供足够信号处理能力的问题,通过采用并行处理技术,可完成多种无线通信标准的基带信号处理。通过分析picoArray系列并行处理器芯片的结构、特点、指令系统和开发工具,获知其可提供远比传统处理器更强大和灵活的处理能力,最后介绍了其在功放线性化中的应用。     

Massive MIMO技术4G化应用研究

作为下一代移动蜂窝网通信（5G）的关键技术之一,Massive MIMO具有极高的频谱效率和能量效率,能大幅提高系统的吞吐量;在其4G化应用研究中,主要挖掘在下行精准波束赋形、上行增强接收分集以及波束三维可调等方面性能;本文通过对Massive MIMO技术4G化标准进度、产品情况及测试情况分析,进一步验证了它的技术优势,指出存在问题和提出解决思路,并总结了Massive MIMO技术4G化应用的推荐场景,为该技术后续研究和规模应用提供一定的指导。     

A Parallel Early-Pruned K-Best MIMO Signal Detector Up to 1.9Gb/s

Multiple inputs multiple outputs orthogonal frequency division multiplexing (MIMO-OFDM) technology is regarded as a promising solution to offer ultra-high data rate in wireless communications. This paper presents a field-programmable gate array (FPGA) implementation of an early-pruned K-Best detection algorithm applicable to ultra-high data throughput MIMO-OFDM communication systems. The algorithm simplifies the computation significantly compared to conventional K-Best algorithm with negligible bit error ratio (BER) degradation. A fully parallel structure is implemented on a FPGA platform, which achieves 1.9Gb/s detection throughput and is about three times over previous implementation. Moreover, a pre-processing method is realized to reduce the number of multipliers inside the detector and shrinks the critical path delay down to 8.32 ns. Together with candidate sharing and early-pruning architecture to further save the hardware cost, a high-speed, compact MIMO signal detector is demonstrated.     

5G Massive MIMO的优化思路探讨

首先重点介绍了5G Massive MIMO关键技术特征,然后分析了该技术与Pre-5G多天线技术的联系与区别。进一步给出了不同广播波束和业务波束配置条件下5G NR的覆盖能力与用户速率感知情况,最后再结合原理分析和测试结论,给出了5G Massive MIMO优化的主要思路,并针对后续优化工作面临的挑战提出了一些建议。     

大规模天线下的数据传输方案研究

Massive MIMO(大规模天线)技术,是未来5G通信中的重要技术。与现有的2、8天线相比,其天线数目可达64、128根,此时,继续采用LTE(长期演进)基于码本的反馈方案,反馈量相当大,UE处理复杂。现提出一种基于子空间反馈的数据传输方案选择方法,可以大幅度减小反馈量,比较简单的实现传输方案选择和多用户配对。     

A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors

A cooperative management scheme for power efficient implementations of real-time operating systems on field-programmable gate-array (FPGA)-based soft processors is presented. Dedicated power management hardware peripherals are tightly coupled to a soft processor by utilizing its configurability. These hardware peripherals manage tasks and interrupts in cooperation with the soft processor, while retaining the real-time responsiveness of the operating system. More specifically, the hardware peripherals perform the following power management functionalities: (1) control the on-chip clock distribution network for driving the soft processor, its hardware peripherals, and the bus interfaces between them; (2) perform task and interrupt management responsibilities of the operating system when the soft processor is turned off; and (3) selectively wake up the soft processor and its hardware components, and put them into proper activation states based on the hardware resource requirements of the tasks under execution. The implementations of two popular real-time operating systems on a state-of-the-art FPGA device are presented. Measurements on an experimental board show that the proposed power management scheme can lead to significant power savings.     

Java Parallel Implementations of Kohonen Self-Organizing Feature Maps

The self-organizing map (SOM) is an unsupervised learning neural network. The goal of this network is to produce a similarity graph of input data. It is a two-dimensional mesh of neurons each with a weight vector. Generally, the network organizes the nodes in the grid into local neighborhoods and the learning process acts as feature classifiers on the input data. The feature map is formed automatically through a cyclic process by comparing input patterns to vectors at each node. No training …     

基于BD-DFT扩展的大规模MIMO码本设计

考虑到大规模多输入多输出（Multiple Input Multiple Output, MIMO）阵列尺寸及外形等因素的限制,本文提出了一种适用于基站采用交叉极化天线面阵的大规模MIMO（Massive MIMO）码本设计方法。该方法综合考虑交叉极化信道的对角化特点和相邻天线之间的相关性,首先设计出与采用交叉极化线阵匹配的码本,进而利用垂直维度天线间的相关性对其进行扩展,最终生成与交叉极化面阵相匹配的码本。仿真结果表明该码本设计方法可使大规模MIMO系统的传输速率和误码率性能得到明显地提升。     

多分辨率多模型目标跟踪方法的三处理机并行实现

介绍了一种用于噪声中机动目标跟踪的小波变换新算法——多分辨率多模型目标跟踪方法。该算法利用小波变换获取多分辨率测量数据,增大了机动检测概率,但需要几倍于传统算法的运算量,难以在实际跟踪系统中实时应用。对此,采用并行处理技术,给出了该算法在包含３个ＣＰＵ的多总线微机系统上井行实现的方法。模拟结果证明了该方法的优良性能,并行处理时间接近传统的单分辨率跟踪算法的处理时间。     

基于高斯树近似的大规模MIMO检测算法

大规模MIMO系统中,基站端复杂的接收信号将导致信号检测困难等问题。该文提出一种基于截断诺依曼级数近似求逆高斯树的低复杂度消息传递算法,该算法在高斯树近似消息传递的过程中利用诺依曼级数近似求解协方差矩阵和最小均方误差估计以降低计算复杂度。仿真结果表明,该文算法在检测性能满足系统需求的同时,也有较低的计算复杂度。     

Massive MIMO pilot assignment optimization based on total capacity

We investigate the effects of pilot assignment in multi-cell massive multiple-input multiple-output systems. When deploying a large number of antennas at base station (BS), and linear detection/precoding algorithms, the system performance in both uplink (UL) and downlink (DL) is mainly limited by pilot contamination. This interference is proper of each pilot, and thus system performance can be improved by suitably assigning the pilot sequences to the users within the cell, according to the desired metric. We show in this paper that UL and DL performances constitute conflicting metrics, in such a way that one cannot achieve the best performance in UL and DL with a single pilot assignment configuration. Thus, we propose an alternative metric, namely total capacity, aiming to simultaneously achieve a suitable performance in both links. Since the PA problem is combinatorial, and the search space grows with the number of pilots in a factorial fashion, we also propose a low complexity suboptimal algorithm that achieves promising capacity performance avoiding the exhaustive search. Besides, the combination of our proposed PA schemes with an efficient power control algorithm unveils the great potential of the proposed techniques in providing improved performance for a higher number of users. Our numerical results demonstrate that with 64 BS antennas serving 10 users, our proposed method can assure a 95%-likely rate of 4.2 Mbps for both DL and UL, and a symmetric 95%-likely rate of 1.4 Mbps when serving 32 users.     

多用户大规模MIMO系统能效资源分配算法

该文针对多用户大规模多输入多输出(MIMO)移动通信上行系统,提出一种基于能效优化的资源分配算法。所提方法在采用最大比合并(MRC)接收情况下,满足用户数据速率和可容忍的干扰水平约束条件下,以最大化系统能效下界为准则建立优化模型。根据分数规划的性质,把原始的分数最优化问题转换成减式的形式,进而采用凸优化的方法,通过联合调整基站端的发射天线数和用户的发射功率来优化能效函数。仿真结果表明,所提算法与穷举算法在能效上的差距不足9%,并且有较好的系统频谱效率性能,同时算法复杂度得到了显著降低。     

一种多处理器并行计算机系统的设计

文章介绍了一种多处理器并行计算机系统，它采用共享存储器互连技术，在结构上类似于分布式系统结构。在软件设计上它采用共享存储器网络技术，使多个处理器之间的通信更方便，软件设计更简单。文章从软硬件设计方面对该系统进行综合论述。     

基于FPGA的可配置MIMO检测器的设计

本文设计了基于FPGA的吞吐率达到100Mbit/s可配置MIMO检测器,可以根据信道估计模块提供的信道状态信息,实现MMSE和QRM-MLD(基于QR分解和M算法的最大似然检测)两种MIMO检测算法间的切换.本设计基于4发4收的MIMO场景,将MMSE的求逆运算与QRM-MLD的QR分解部分共用硬件资源,在Xilinx的FPGA上实现的结果表明,本设计与两个独立的检测器相比,大大节省了FPGA的乘法器资源和逻辑资源.     

一种基于有序统计的MIMO雷达CFAR检测器

针对多输入多输出(MIMO)雷达的体制特点,提出了一种基于有序统计的MIMO雷达CFAR检测器(LCIOSOS-CFAR),给出了虚警概率与检测概率的表达式;然后在各种杂波背景下对检测器性能进行了仿真分析,并与经典的CA-CFAR检测器进行比较.仿真结果表明,LCIOSOS-CFAR检测器在均匀杂波背景下较CA-CFAR有较小损失,在多目标干扰环境下较CA-CFAR性能改善明显,在杂波边缘背景下虚警峰值小于CA-CFAR,实际应用中具有较强的鲁棒性.文中还分析了序值选取对LCIOSOS-CFAR检测性能的影响.     

海量数据并行压缩算法研究

由于计算机技术的广泛应用及生产技术的飞速进步在某些数据密集型的生产部门，处理生产数据往往需要很大的计算量，与之对应的存储空间也大。海量数据的压缩存储涉及到两种技术：一是数据压缩技术。另一个是并行编程技术。探索如何把这两方面结合起来，使海量数据的压缩存储从理论应用于实践。