Improved method of digital/analogue and analogue/digital conversion

The letter describes a method of rapidly interpolating between the levels of a DAC. Having inherent monotonicity, the method offers major advantages in analogue/digital and digital/analogue conversion in a certain important range of applications.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.     

Physical modeling of lateral scaling in bipolar transistors

The dependence of important transistor characteristics, such as transit frequency, on emitter width and length is modeled on a physical basis. Closed-form explicit analytical equations are derived for modeling the emitter size dependence of the low-current minority charge and transit time, the critical current indicating the onset of high injection in the collector, and the stored minority charge in the collector at high injection. These equations are suited for application in various compact transistor models such as the SPICE Gummel-Poon model (SGPM) as well as the advanced models HICUM and MEXTRAM. As demonstrated by two- and three-dimensional device simulation and measurements, combination of the derived equations with HICUM results in accurate prediction of the characteristics of transistors with variable emitter length and width. As a consequence, the new model makes the conventional transistor library unnecessary and offers bipolar circuit designers the flexibility to use the transistor size that fits the application best     

Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

Improved emitter transit time using AlGaAs-GaInP composite emitterin GaInP/GaAs heterojunction bipolar transistors

A new emitter structure based on composite graded AlGaAs-GaInP approach is described, which allows significant reduction of CBE and improved high-frequency performance. A theoretical study of the composite and conventional emitter HBTs is performed to prove the superiority of composite emitter HBTs using Monte Carlo simulation of their transport properties. The self-aligned HBTs fabricated in this study are grown by CBE with TBA/TBP precursors. The current gain cutoff frequency (f_T) was 62 GHz for the composite emitter design HBT, and 45 GHz for conventional emitter design HBT. The CBE achieved with the composite emitter designs was at least 3 times lower than that of conventional designs and does not show significant variation with collector current. This leads to enhanced f_T characteristics by 15% for composite emitter HBT designs and confirms the theoretical expectations     

Origin of 1/f noise in lateral PNP bipolar transistors

1/f noise was measured on lateral bipolar PNP transistors over a temperature range of 220<T<450 K. Noise power spectral density measurements were performed simultaneously across two resistors connected in series with base and collector. The equivalent base current noise source S_IB has two dominant components. One is S_IBE that is between the base and the emitter, in parallel with r_π. The other is S_IBC coming from the surface recombination current at the neutral base, between the base and the collector. The extracted S_IB exhibited a near square law dependence on base current I_B. The noise remained nearly constant when the temperature was below 310 K. However, it presented strong temperature dependence when the temperature was beyond 310 K. Two different models are proposed for the noise in different temperature regions. For the high temperature region, the surface recombination velocity fluctuation model is proposed, which indicates that the noise is coming from the fluctuations in the surface recombination velocity at the neutral base surface. The tunneling assistant trapping model is responsible for the low temperature region, where the noise source is the carrier trapping–detrapping by the defects in the spacer oxide covering the surface of the depletion layer.     

Improved cutoff frequency in vertical bipolar transistors fabricated with focused ion beam lateral base profiles

Improved high-frequency performance in vertical bipolar transistors in which the active base region is fabricated with focused ion beam (FIB) lateral doping profiles is demonstrated. Profiles which reduce base resistance, current crowding, and high-level injection effects have the most significant effect on high-frequency characteristics.     

Collector-top GaAs/AlGaAs heterojunction bipolar transistors for high-speed digital ICs

GaAs/AlGaAs collector-top heterojunction bipolar transistors with magnesium and phosphorus double-implanted external bases were fabricated. A cutoff frequency of 17 GHz and a gate delay time of 63 ps for DCTL were obtained. These results indicate the potential of collector-top HBTs for high-speed ICs.     

On buried oxide effects in SOI lateral bipolar transistors

We report buried oxide effects on the Silicon-On-Insulator Lateral Bipolar Transistor (SOILBT) performance by two-dimensional (2-D) numerical simulation and experiments. An early punchthrough is observed in SOILBT compared to the bulk due to the presence of buried oxide. In addition to dopant segregation into the buried oxide, the presence of buried oxide also diverts some electric field lines emanating from collector toward substrate, due to 2-D distribution of field, leaving fewer across the base region and hence increased depletion widths and punchthrough. One-dimensional (1-D) depletion approximation fails to predict this punchthrough. To establish the evidence of buried oxide induced punchthrough without dopant segregation effect, simple and yet novel measurement techniques are proposed to extract effective base width and base doping concentration near the buried oxide-silicon film interface using the parasitic MOSFET in SOILBT. Good agreement between 2-D simulation and experimental results was observed. Finally design curves are generated using 2-D numerical simulation for different base doping and buried oxide thicknesses on SOI substrates     

Half-micrometre-base lateral bipolar transistors made in thin silicon-on-insulator films

NPN and PNP lateral bipolar transistors having a base length shorter than 0.5 ?m have been made in thin (100 nm) silicon-on-insulator films. Current gains of 75 and 40 have been obtained in NPN and PNP devices, respectively. Measurements indicate a base generation lifetime of 1 ?s, and leakage currents of a fraction of a picoampere have been measured. The device fabrication is compatible with an SOI CMOS fabrication process.     

High-performance analogue multiplier based on the characteristics of bipolar transistors

The analogue multiplier described, while having a bandwidth similar to that of the long-tail-pair transconductance multiplier, has considerably better performance as regards nonlinearity, zero stability and dynamic range.     

Yield improvement using configurable analogue transistors

Continued process scaling has led to significant yield and reliability challenges for today's designers. Analogue circuits are particularly susceptible to poor variation, driving the need for new yield resilient techniques in this area. A new configurable analogue transistor structure and supporting methodology that facilitates variation compensation at the post-manufacture stage is described. The approach has demonstrated significant yield improvements and can be applied to any analogue circuit.     

Analysis and modelling of lateral heterostructure field-effect bipolar transistors

Lateral heterostructure field-effect bipolar transistors (LH-FEBTs) are thin-film transistors that have a distinct heterojunction located roughly midway between the source and drain contacts, with a p-type semiconductor on one side of the junction, and an n-type semiconductor on the other. These devices have potential in display applications but are relatively new to the research community. In this paper, we describe the fabrication of a hybrid LH-FEBT using pentacene and ZnO as the p- and n-type semiconductors, respectively, and describe its unusual bell-shaped electrical transfer characteristics. Using an equivalent circuit approach, we analyse quantitatively how the main features of the current–voltage curves relate to semiconductor properties such as carrier mobility and threshold voltage – information that is essential to the design of such devices.     

Improved circuit-device interface for microwave bipolar power transistors

Several improvements in the mounting and interconnection of bipolar microwave power transistors are described. A plated heat sink applied to thinned transistor pellets decreases the junction temperature for a given dissipation level by approximately a factor of 2. A new, low-parasitic-BeO carrier provides improved power sharing between cells and better high-frequency performance as illustrated by a CW power output of 4 W at 5 GHz with 6-dB gain. Finally, a new etched-line interconnection system is discussed that promises to become a highly reproducible, low-cost replacement for the widely used, but troublesome, multiple wire bonds.     

双极晶体管和肖特基二极管改进技术

设计进步及封装技术的改进使开发优化的分立半导体器件成为可能,例如低饱和电压晶体管及超低正向压降肖特基整流二极管。此类新器件可满足当争电子产品在散热、效率,空间占用和成本方面的高要求．对于便携式电池供电设备(如笔记本电脑、数码相机)及汽车中的负载切换和电源系统,此粪新器件是首选的解决方案。     

Improved second breakdown of integrated bipolar power transistors

This paper presents two new power bipolar transistor structures With greatly increased forward Second breakdown values without saturation voltage degradation. These structures, labeledS1 andS2, were obtained with slight modification of the output stages of an IC power amplifier and without complicating the standard IC process. The design concepts developed in this paper were applied to power transistors fabricated using two different processes already in production: processA(V_{CEO(sus)} gt 50V) and processB(V_{CEO(sus)} gt 80V). Measurements have Shown that an improvement of three times for dc conditions and four times or more for single pulses duration of less than 1 ms can be obtained for structureS1 while structureS2 is able to achieve the proportionality between power silicon area and power levels. Experimental temperature distributions over emitter area and some theoretical calculations for the steady-state condition are given.     

Fully differential operational amplifiers using CMOS compatible lateral bipolar transistors with improved common-mode regulation

A new bias circuit for a CMOS compatible lateral bipolar transistor differential pair is presented. The circuit compensates for all process and bias dependent variations of the lateral collector current to emitter current ratio alpha . Experimental results show that its application to a fully differential amplifier improves the precision of the common-mode output voltage regulation by at least an order of magnitude.<>     

Heterojunction bipolar transistors using Si-Ge alloys

Advanced epitaxial growth techniques permit the use of pseudomorphic Si_1-xGe_x alloys in silicon technology. The smaller bandgap of these alloys allows for a variety of novel band-engineered structures that promise to enhance silicon-based technology significantly. The authors discuss the growth and properties of pseudomorphic Si_1-xGe_x structures and then focus on their applications, especially the Si_1-xGe_x -base heterojunction bipolar transistor (HBT). They show that HBTs in the Si_1-xGe_x system allow for the decoupling of current gain and intrinsic base resistance. Such devices can be made by using a variety of techniques, including molecular-beam epitaxy and chemical vapor deposition. The authors describe the evolution of fabrication schemes for such HBTs and describe the DC and AC results obtained. They show that optimally designed HBTs coupled with advanced bipolar structures can provide performance leverage     

Digital integrated circuit using GaInAs/InP heterojunction bipolar transistors

A divider circuit using GaInAs/InP heterojunction bipolar transistors is reported for the first time. This is the first monolithic digital integrated circuit using these devices. The divider has been clocked at 5 GHz, which is the fastest toggle rate for a bipolar circuit on InP.<>     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible