Reliability of wire-bonding and solder joint for high temperature operation of power semiconductor device

Thick Al wires bonded on chips of power semiconductor devices were examined for thermal cycle tests, then the bonded joints were cut using microtome method, after that those were observed by scanning electron microscope and analyzed by electron back scattered diffraction. Some cracks were observed between Al wires and the chips, unexpectedly the crack lengths were almost constant for −40/150 °C, −40/200 °C and −40/250 °C tests. It is considered that re-crystallization has been progressed during the high temperature side of the thermal cycle tests.Furthermore, joint samples were prepared using high temperature solders such as Zn–Al and Bi with CuAlMn, Direct Bonded Copper insulated substrates and Mo heatsinks. The fabricated samples were evaluated by scanning acoustic microscope before and after thermal cycle tests. Consequently, almost neither serious damages nor delaminations were observed for −40/200 °C and −40/250 °C tests.     

Fatigue analysis of miniaturized lead-free solder contacts based on a novel test concept

The paper presents the method of generating lifetime-prediction-laws on special prepared very stiff specimen. The combination of thin- and thick-film technology allows building up test samples on ceramic very similar to electronic packages including the measurement issues. Influences of pad surface metallurgy, microstructure of solder, ineutectic solder alloys and assembly process parameter are regarded now. The investigation objects provide monitoring of electrical and mechanical damage process of SnAgCu solder bump. Different thermo-mechanical loads will be applied in temperature ranges of 0 to +80 °C, −40 to +125 °C and −50 to +150 °C, where the temperature gradient and cycle frequency also vary. A Variation of four different chip sizes allows the determination of fatigue laws for each temperature profile, to be able to compare in between them. The results of these tests will give universal lifetime-prediction laws for SnAgCu base solder joints. Main goals are to find coefficients for lifetime prediction models such as Coffin–Manson- or Norris–Landzberg-relation, which are transferable in between different electronic packages.     

Low temperature delamination of plastic encapsulated microcircuits

Plastic encapsulated microcircuits (PEMs) are increasingly being used in applications requiring operation at temperatures lower than the manufacturer’s recommended minimum temperature, which is 0°C for commercial grade components and −40°C for industrial and automotive grade components. To characterize the susceptibility of PEMs to delamination at these extreme low temperatures, packages with different geometries, encapsulated in both biphenyl and novolac molding compounds, were subjected to up to 500 thermal cycles with minimum temperatures in the range −40 to −65°C in both the moisture saturated and baked conditions. Scanning acoustic microscopy revealed there was a negligible increase in delamination at the die-to-encapsulant interface after thermal cycling for the 84 lead PQFPs encapsulated in novolac and for both 84 lead PQFPs and 14 lead PDIPs encapsulated in biphenyl molding compound. Only the 14 lead novolac PDIPs exhibited increased delamination. Moisture exposure had a significant effect on the creation of additional delamination.     

Thermal fatigue endurance of collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies

The behavior of thermomechanically loaded collapsible 95.5Sn4Ag0.5Cu spheres in LTCC/PWB assemblies with high (LTCC/FR-4; ΔCTE 10 ppm/°C) and low (LTCC/Arlon; ΔCTE < 10 ppm/°C) global thermal mismatches was studied by exposing the assemblies into two thermal cycling tests. The characteristic lifetimes of the LTCC/FR-4 assemblies, tested over the temperature ranges of 0–100 °C and −40 to 125 °C, were 1475 and 524 cycles, respectively, whereas the corresponding values of the LTCC/Arlon assemblies were 5424 and 1575 cycles. According to the typical requirements for the industrial lifetime duration of solder joints, the former values are inadequate, whereas the latter are at an acceptable level in a few cases. Furthermore, the global thermal mismatch affected the thermal fatigue behavior of the 95.5Sn4Ag0.5Cu spheres in the temperature range of −40 to 125 °C.     

Properties of low temperature Sn–Ag–Bi–In solder systems

The metallurgical and mechanical properties of Sn–3.5 wt%Ag–0.5 wt%Bi–xwt%In (x = 0–16) alloys and of their joints during 85 °C/85% relative humidity (RH) exposure and heat cycle test (−40–125 °C) were evaluated by microstructure observation, high temperature X-ray diffraction analysis, shear and peeling tests. The exposure of Sn–Ag–Bi–In joints to 85 °C/85%RH for up to 1000 h promotes In–O formation along the free surfaces of the solder fillets. The 85°C/85%RH exposure, however, does not influence the joint strength for 1000 h. Comparing with Sn–Zn–Bi solders, Sn–Ag–Bi–In solders are much stable against moisture, i.e. even at 85 °C/85%RH. Sn–Ag–Bi–In alloys with middle In content show severe deformation under a heat cycles between −40 °C and 125 °C after 2500 cycles, due to the phase transformation from β-Sn to β-Sn + γ-InSn₄ or γ-InSn₄ at 125 °C. Even though such deformation, high joint strength can be maintained for 1000 heat cycles.     

CCGA packages for space applications

Commercial-off-the-shelf (COTS) area array packaging technologies in high reliability versions are now being considered for applications, including use in a number of NASA electronic systems being utilized for both the Space Shuttle and Mars Rover missions. Indeed, recently a ceramic package version specifically tailored for high reliability applications was used to provide the processing power required for the Spirit and Opportunity Mars Rovers built by NASA-JPL. Both Rovers successfully completed their 3-months mission requirements and continued exploring the Martian surface for many more moths, providing amazing new information on previous environmental conditions of Mars and strong evidence that water exists on Mars.Understanding process, reliability, and quality assurance (QA) indicators for reliability are important for low risk insertion of these newly available packages in high reliability applications. In a previous investigation, thermal cycle test results for a non-functional daisy-chained peripheral ceramic column grid array (CCGA) and its plastic ball grid array (PBGA) version, both having 560 I/Os, were gathered and are presented here. Test results included environmental data for three different thermal cycle regimes (−55/125 °C, −55/100 °C, and −50/75 °C). Detailed information on these—especially failure type for assemblies with high and low solder volumes—are presented. The thermal cycle test procedure followed those recommended by IPC-9701 for tin–lead solder joint assemblies. Its revision A covers guideline thermal cycle requirements for Pb-free solder joints. Key points on this specification are also discussed.In a recent investigation a fully populated CCGA with 717 I/Os was considered for assembly reliability evaluation. The functional package is a field-programmable gate array that has much higher processing power than its previous version. This new package is smaller in dimension, has no interposer, and has a thinner column wrapped with copper for reliability improvement. This paper will also present thermal cycle test results for assemblies of this and its plastic package version with 728 I/Os, both of which were exposed to four different cycle regimes. Two of these cycle profiles are specified by IPC-9701A for tin–lead, namely, −55 to 100 °C and −55 to 125 °C. One is a cycle profile specified by Mil-Std-883, namely, −65/150 °C, generally used for ceramic hybrid packages screening and qualification. The last cycle is in the range of −120 to 85 °C, a representative of electronic systems directly exposed to the Martian environment without use in a thermal control enclosure. Per IPC-9701A, test vehicles were built using daisy chain packages and were continuously monitored and/or manually checked for opens at intervals. The effects of many process and assembly variables—including corner staking commonly used for improving resistance to mechanical loading such as drop and vibration loads—were also considered as part of the test matrix. Optical photomicrographs were taken at various thermal cycle intervals to document damage progress and behavior. Representative samples of these are presented along with cross-sectional photomicrographs at higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for packages.     

Rapid power cycling of flip-chip and CSP components on ceramic substrates

Power cycling has been done for flip-chip and CSP components solder joined onto ceramic substrates. Cycle periods as short as 1 min were applied in the experiments where the chip temperature varied between about 30°C in the power off-state and 100–150°C in the power on-state. Disconnections of the joints were found after 4000–17 000 power cycles. The flip-chip components joined onto low temperature cofired ceramic substrate showed slightly better reliability than the components joined onto alumina substrate. Most of the samples showed clear effects of deterioration of the joints seen as increasing chip temperature for power on-state. The experimental results are compared with calculations based on modified Coffin–Manson equation as well as with one-dimensional simulations.     

Effects of TMF heating rates on damage accumulation and resultant mechanical behavior of Sn–Ag based solder joints

Solder joint reliability depends on several service parameters such as temperature extremes encountered, dwell times at these temperatures, and the ramp-rates representing the rate at which the temperature changes are imposed. TMF of Sn–Ag based solder alloy joints of realistic dimensions were carried out with dwell of 115 min and 20 min at 150 °C and −15 °C, respectively. Different heating rates were obtained by controlling the power input during heating part of TMF cycles. Surface damage and residual mechanical strength of these solder joints were characterized after 0, 250, 500, and 1000 TMF cycles to evaluate the role of TMF heating rate on the solder joint integrity.     

Lead-free 0201 manufacturing, assembly and reliability test results

The trend towards smaller, faster and cheaper electronic devices has led to an increase in the use of 0201 (L  0.02 in.; W  0.01 in.) and even smaller sized passive components. The size advantages of the 0201 component make it a popular choice among design engineers but not among manufacturing engineers. From a manufacturing perspective, the size of the 0201 package poses significant challenges to the printed circuit board (PCB) assembly process. The many challenges with 0201 assembly can be attributed to the solder paste volume, pad design, aperture design, board finish, type of solder paste, pick-and-place and reflow profile. If these factors are not optimized, they will introduce undesirable manufacturing defects. The small size of 0201 packages and undetected manufacturing defects will also raise concerns about their second level interconnect reliability, especially for lead-free solder alloys and surface finishes, with new processes and higher reflow requirements. To determine the optimum conditions, a design-of-experiment (DOE) study was carried out to investigate the effects of these parameters on assembly defects and solder joint reliability.This paper presents the test results and comparative literature data on the influence of a few key manufacturing parameters and defects associated with the 0201 component using lead-free and tin–lead solder alloys. Data pertaining to component shear strength before and after isothermal aging at 150 °C and intermetallic growth up to 500 h of aging are presented. A number of test vehicles were also subjected to thermal cycling (1500 cycles) in the range of −55/100 °C to determine the solder fatigue behavior. Shear test results for test vehicles subjected to thermal cycling is also presented. In addition, optical microscopy analysis of solder joint behavior during thermal cycling showing the progress of the solder damage and cross-sectional photos taken at 1500 cycles is included.     

Pb-free high temperature solders for power device packaging

Reliabilities of joints for power semiconductor devices using a Bi-based high temperature solder has been studied. The Bi-based solder whose melting point is 270 °C were prepared by mixing of the CuAlMn particles and molten Bi to overcome the brittleness of Bi. Then, joined samples using the solder were fabricated and thermal cycling tests were examined. After almost 2000 test cycles of −40/200 °C test, neither intermetallic compounds nor cracks were observed for CTE (Coefficient of Thermal Expansion) matched sample with Cu interface. On the other hand, certain amount of intermetallic compound such as Bi₃Ni was found for a sample with Ni interface. In addition, higher reliability of this solder than Sn-Cu solder was obtained after −40/250 °C test. Furthermore, an example power module structure using double high temperature solder layers was proposed.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin–bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin-plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling

Growth behavior of tin whiskers from pure tin and tin-bismuth plated leadframe (LF) packages for elevated temperature and high humidity storages and during thermal cycling was observed. In the storage at 60 °C/93% relative humidity (RH) and 85 °C/85%RH the galvanic corrosion occurred at the outer lead toes and shoulders where the base LF material is exposed, forming tin oxide layers of SnO₂. The corroded layers spread inside the film and formed whiskers around the corroded islands. Many whiskers were observed to grow from grain boundaries for the Fe–42Ni alloy (alloy42) LF packages. It was confirmed that the corrosion tends to occur on the side surfaces of outer leads adjacent to the mold flash. The contribution of ionic contaminants in epoxy mold compound (EMC) to the corrosion was not identified. During thermal cycling between −65 °C and +150 °C whiskers grew out of as-deposited grains for pure tin plated alloy42 LF packages and they grew linearly with an increase of number of cycle. Growth mechanisms of the whiskers from grain boundaries and as-deposited grains were discussed from the deformation mechanism map for tin and mathematical calculation with a steady-state diffusion model.     

Effect of primary creep and plasticity in the modeling of thermal fatigue of SnPb and SnAgCu solder joints

It has been conventional to simplify the thermo-mechanical modeling of solder joints by omitting the primary (transient) contributions to total creep deformation, assuming that secondary (steady-state) creep strain is dominant and primary creep is negligible. The error associated with this assumption has been difficult to assess because it depends on the properties of the solder joint and the temperature–time profile. This paper examines the relative contributions of plasticity, primary and secondary creep in Sn40Pb and Sn3.8Ag0.7Cu solders using the analysis of a trilayer solder joint structure with finite elements and a newly developed finite difference technique. The influences of temperature amplitude and ramp rate have been quantified. It was found that for the thermal profiles considered, the role of plasticity was negligible for trilayer assemblies with SnPb and SnAgCu solder interlayers. Furthermore, when primary creep was included for SnAgCu, the temperature-dependent yield strength was not exceeded and no plastic strains resulted. Neglect of primary creep can result in errors in the predicted stress and strain of the solder joint. Damage metrics based on the stabilized stress vs. strain hysteresis loop, for symmetric 5 min upper/lower dwell periods, differ widely when primary creep is considered compared to the secondary-only creep model. Creep strain energy density differences between the secondary-only and primary plus secondary creep models for SnPb were 32% (95 °C/min–Δ165 °C thermal profile), 32% (95 °C/min–Δ100 °C) and 35% (14 °C/min–Δ100 °C); similarly for SnAgCu, the differences were 29% (95 °C/min–Δ165 °C), 46% (95 °C/min–Δ100 °C) and 58% (14 °C/min–Δ100 °C). Accumulated creep strain differences between the secondary-only and primary plus secondary creep models for SnPb were 21% (95 °C/min–Δ165 °C), 25% (95 °C/min–Δ100 °C) and 25% (14 °C/min–Δ100 °C); similarly for SnAgCu the differences were 82% (14 °C/min–Δ100 °C), 89% (95 °C/min–Δ100 °C) and 100% (95 °C/min–Δ165 °C). In turn, these discrepancies can lead to errors in the estimation of the solder thermal fatigue life due to the changing proportion of primary creep strain to total inelastic strain under different thermal profiles, particularly for SnAgCu.     

Advanced electrical and stability characterization of untrimmed and variously trimmed thick-film and LTCC resistors

As-fired thick-film resistors have the resistance tolerance within ±20% and this tolerance is increased for smaller components. Therefore the novel trimming methods are necessary for microresistors, especially when they are embedded in LTCC substrate. This paper compares electrical (normalized temperature dependence of resistance, low frequency noise) and stability properties (relative resistance drift, changes of current noise index) of untrimmed, voltage pulse trimmed and laser trimmed unglazed thick-film resistors after step-increased long-term thermal ageing at 162 °C, 207 °C and 253 °C. Moreover the effect of long term exposure (1000 h, 125 °C) and thermal shocks (1000 shocks between −55 °C and 125 °C) is analysed for untrimmed and voltage pulse trimmed buried LTCC resistors.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

Effects of bonding temperature on the properties and reliabilities of anisotropic conductive films (ACFs) for flip chip on organic substrate application

The effects of bonding temperatures on the composite properties and reliability performances of anisotropic conductive films (ACFs) for flip chip on organic substrates assemblies were studied. As the bonding temperature decreased, the composite properties of ACF, such as water absorption, glass transition temperature (T_g), elastic modulus (E′) and coefficient of thermal expansion (α), were improved. These results were due to the difference in network structures of cured ACFs which were fully cured at different temperatures. From small angle X-ray scattering (SAXS) test result, ACFs cured at lower temperature, had denser network structures. The reliability performances of flip chip on organic substrate assemblies using ACFs were also investigated as a function of bonding temperatures. The results in thermal cycling test (−55 °C/+150 °C, 1000 cycles) and PCT (121 °C, 100% RH, 96 h) showed that the lower bonding temperature resulted in better reliability of the flip chip interconnects using ACFs. Therefore, the composite properties of cured ACF and reliability of flip chip on organic substrate assemblies using ACFs were strongly affected by the bonding temperature.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Ball grid array reliability assessment for aerospace applications

Reliability of ball grid arrays (BGAs) was evaluated with special emphasis on space applications. This work was performed as part of a consortium led by the Jet Propulsion Laboratory (JPL) to help build the infrastructure necessary for implementing this technology. Nearly 200 test vehicles, each with four package types, were assembled and tested using an experiment design. The most critical variables incorporated in this experiment were package type, board material, surface finish, solder volume, and environmental condition. The packages used for this experiment were commercially available packages with over 250 I/Os including both plastic and ceramic BGA packages.The test vehicles were subjected to thermal and dynamic environments representative of aerospace applications. Two different thermal cycling conditions were used, the JPL cycle ranged from −30°C to 100°C and the Boeing cycle ranged from −55°C to 125°C. The test vehicles were monitored continuously to detect electrical failure and their failure mechanisms were characterized. They were removed periodically for optical inspection, scanning electron microscopy (SEM) evaluation, and cross-sectioning for crack propagation mapping. Data collected from both facilities were analyzed and fitted to distributions using the Weibull distribution and Coffin–Manson relationships for failure projection. This paper will describe experiment results as well as those analyses.     

Qualification approaches and thermal cycle test results for CSP/BGA/FCBGA

Qualification of newly developed multifunctional electronic packages, e.g. system in a package (SIP), are becoming complex at the package level and even more at the assembly and system levels. After many years of data collection, just recently industry agreed to release an industry-wide specification for single die area array package assembly qualification.Probability risk assessment, being implemented by NASA for space flight missions, may be narrowed at the element level for advanced electronic systems and SIP, and further narrowed at the electronic subsystem level. This paper will review the key elements of an industry-wide specification recently published by the IPC (association connecting electronics industries). It will report on a few other unique qualification approaches that are currently being either implemented or developed for risk reduction in high reliability applications. Risk level assessment based 2-P, 3-P, and LogNormal distributions will be compared for plastic ball grid array (PBGA) and flip chip BGA (FCBGA). For this case, risks are compared using cycles-to-failures (CTFs) test results for temperature ranges of −30 to 100 °C and 0 to 100 °C (two profiles).In addition, CTFs up to 1,500 cycles in the range of −55 to 125 °C for a 784 I/O FCBGA (flip chip BGA, a 175 I/O FPBGA (fine pitch BGA)), and a 313 I/O PBGA (plastic BGA) are compared. Inspection results along with scanning electron microscopy and optical cross-sectional photos revealing damage and failure mechanisms are also included.     

Thermally induced deformation of solder joints in real packages: Measurement and analysis

The paper presents a hybrid experimental and analytical approach to track the deformation of solder joints in an electronic package subject to a thermal process. The solder joint strain is directly measured using a computer vision technique. The strain measurement is analyzed following an approach that is devised based on an established solder constitutive relation. The analysis leads to the determination of the solder joint stress and in turn, to the separation of the elastic, plastic and creep strain from the measured total strain. The creep strain rate and stress–strain hysteresis loop are also obtained. Two case studies are presented to illustrate the applications and to show the viability of the approach. Each case involves a resistor package with SAC (Sn95.5Ag3.8Cu0.7) solder joints, which is subjected to a temperature variation between ambient and 120 °C. The results confirm that shear is a dominant strain component in such solder joints. The shear strain varies nearly in phase with the temperature whereas the shear stress exhibits a different trend of variation due to stress relaxation. The peak shear stress of around 10 MPa to 15 MPa are found, which occur at near 70 °C in both cases, when the temperature ramps up at approximately 3 °C/min. The creep shear strain goes up to 0.02 and accounts for over 80% of the total shear strain. The creep strain rate is in the order of magnitude of 10⁻⁵ s⁻¹. Responding to the temperature cycling with such moderate rate, the creep strain shows modest ratcheting while the stress–strain hysteresis stabilizes in two cycles.