Low-temperature polysilicon TFT with gate oxide grown byhigh-pressure oxidation

Polysilicon thin-film transistors (TFTs) were fabricated with the maximum processing temperature limited to 650°C. Best results were obtained when the gate oxide was grown by a two-step high-pressure oxidation process, using high-pressure steam and then dry oxygen both at 15 atm and 650°C. The TFTs exhibit a mobility of 34 cm²/V×s, threshold voltage of 3.5 V, leakage current below 0.01 pA/μm, subthreshold slope of 0.18 V/decade, and an ON/OFF ratio of over eight orders of magnitude. These values are comparable to those obtained with conventional polysilicon TFTs using high-temperature thermal oxidation     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

Fabrication of SOS MOSFETs using two-step doping with excimer laser

Using two-step doping with excimer laser, p-channel MOSFETs were fabricated in thin silicon films on sapphire (SOS). Source and drain p ⁺ layers were formed using two-step doping with only one melting pulse of excimer laser. Devices were processed at room temperature except for the LPCVD gate oxide deposition at 450°C. High-quality thin film transistors (TFTs) were fabricated with on/off current ratio of 7 and a field effect hole mobility of 145 cm²/V s     

Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

1.1 kV 4H-SiC power UMOSFETs

Silicon Carbide (4H-SiC), power UMOSFETs were fabricated and characterized from room temperature to 200°C. The devices had a 12-μm thick lightly doped n-type drift layer, and a nominal channel length of 4 μm. When tested under Fluorinert^TM at room temperature, blocking voltages ranged from 1.0 kV to 1.2 kV. Effective channel mobility ranged from 1.5 cm²/V.s at room temperature with a gate bias of 32 V (3.5 MV/cm) up to 7 cm²/V.s at 100°C with an applied gate bias of 26 V (2.9 MV/cm). Specific on-resistance (R_on,sp) was calculated to be as low as 74 mΩ.cm² at 100°C under the same gate bias     

Low-temperature (⩽550°C) fabrication of poly-Si thin-filmtransistors

High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550°C. This process features the use of polycrystalline Si_0.5Ge_0.5 for the gate material and high-dose H⁺ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm²/V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600°C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

Suppression of the boron penetration induced dielectric degradationby using a stacked-amorphous-silicon film as the gate structure forpMOSFET

This work proposes a stacked-amorphous-silicon (SAS) film as the gate structure of the p⁺ poly-Si gate pMOSFET to suppress boron penetration into the thin gate oxide. Due to the stacked structure, a large amount of boron and fluorine piled up at the stacked-Si layer boundaries and at the poly-Si/SiO₂ interface during the annealing process, thus the penetration of boron and fluorine into the thin gate oxide is greatly reduced. Although the grain size of the SAS film is smaller than that of the as deposited polysilicon (ADP) film, the boron penetration can be suppressed even when the annealing temperature is higher than 950°C. In addition, the mobile ion contamination can be significantly reduced by using this SAS gate structure. This results in the SAS gate capacitor having a smaller flat-band voltage shift, a less charge trapping and interface state generation rate, and a larger charge-to-breakdown than the ADP gate capacitor. Also the Si/SiO₂ interface of the p⁺ SAS gate capacitor is much smoother than that of the p⁺ SAS gate capacitor     

Effects of trap-state density reduction by plasma hydrogenation inlow-temperature polysilicon TFT

The reduction of trap-state densities by plasma hydrogenation in n-channel polysilicon thin-film transistors (poly-TFTs) fabricated using a maximum temperature of 600°C has been studied. Hydrogenated devices have a mobility of ~40 cm²/V×5, a threshold voltage of ~2 V, an inverse subthreshold of ~ 0.55 V/decade, and a maximum on/off current ratio of 5×10⁸. The effective channel length decreases by ~0.85 μm after a short hydrogenation which may be attributed to the activation of donors at trap states near the source/drain junctions. Trap-state densities decrease from 1.6×10¹² to 3.5×10¹¹ cm^-2 after hydrogenation, concomitant with the reduction of threshold voltage. Using the gate lengths at which the trap-state densities deviate from the long-channel values as markets for the leading edge of passivation, the apparent hydrogen diffusivity is found to be 1.2×10^-11 cm²/s at 350°C in the TFT structure     

Preparation of thin-film transistors with chemical bath depositedCdSe and CdS thin films

The authors have fabricated the thin-film transistor (TFT) with CdSe and CdS semiconductor thin films, prepared by a low temperature chemical bath deposition (CBD) method, as an active layer. The ON-current values of the CdSe-TFTs and CdS-TFTs at a gate bias of 10 V and a source-drain voltage of 10 V are about 100 μA and 5 μA, respectively. The OFF-current values of the CdSe-TFTs and CdS-TFTs at the source-drain voltage of 10 V are less than 10 pA. The fabricated CdSe-TFTs exhibited a field effect mobility of 15 cm²/V-s, threshold voltage of 3.5 V, subthreshold slope of 0.5 V/dec., and ON/OFF current ratios exceed 10⁷. A field effect mobility of I cm ²/V-s, a threshold voltage of 2.6 V, a subthreshold slope of 0.6 V/dec., and an ON/OFF current ratios exceed 10⁶ were observed for CdS TFTs     

Digital CMOS IC's in 6H-SiC operating on a 5-V power supply

A CMOS technology in 6H-SiC utilizing an implanted p-well process is developed. The p-wells are fabricated by implanting boron ions into an n-type epilayer. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells using a thermally grown gate oxide. The resulting NMOS devices have a threshold voltage of 3.3 V while the PMOS devices have a threshold voltage of -4.2 V at room temperature. The effective channel mobility is around 20 cm ²/Vs for the NMOS devices and around 7.5 cm²/Vs for the PMOS devices. Several digital circuits, such as inverters, NAND's, NOR's, and 11-stage ring oscillators are fabricated using these devices and exhibited stable operation at temperatures ranging from room temperature to 300°C. These digital circuits are the first CMOS circuits in 6H-SiC to operate with a 5-V power supply for temperatures ranging from room temperature up to 300°C     

High-performance polycrystalline SiGe thin-film transistors usingAl2O3 gate insulators

The use of aluminum oxide as the gate insulator for low temperature (600°C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N₂O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al₂O₃), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al₂O₃ gate dielectric layers. Typically, a field effect mobility of 47 cm²/Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3×10⁵ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al₂ O₃ and the SiGe channel layer is sufficiently passivated to make Al₂O₃ a better alternative to grown or deposited SiO₂ for SiGe field effect devices     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

Development of high-performance polycrystalline silicon thin-filmtransistors (TFTs) using defect control process technologies

High-performance polycrystalline Si (poly-Si) thin-film transistors (TFTs) were successfully fabricated on a glass substrate below 425°C by introducing defect control process technologies. The defects in the laser crystallized poly-Si films were terminated by an oxygen plasma treatment to the film and the defects at the SiO₂ /Si interface were controlled by a gate SiO₂ film formation using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). As a result, high n-channel mobility of 309 cm²V^-1s^-1, low threshold voltage of 1.12 V and low subthreshold swing of 250 mV/decade were obtained. In addition, it was demonstrated that the defect control process is quite effective to minimize the variation of TFT characteristics