多晶硅薄膜的新型激光晶体制备方法

采用两步激光晶化方法制备了多晶硅薄膜,其晶粒尺寸为１．１μｍ,比用传统单步晶化制备的薄膜晶粒尺寸大,表明该方法法对扩大晶粒尺寸很有效。拉曼光谱分析表明０．３０Ｊ／ｃｍ＾２晶化的薄膜结晶程度已很高。     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

多晶硅薄膜的新型激光晶化制备方法

采用两步激光晶化方法制备了多晶硅薄膜 ,其晶粒尺寸为 1.1μm,比用传统单步晶化制备的薄膜晶粒尺寸大 ,表明该方法对扩大晶粒尺寸很有效。拉曼光谱分析表明 0 .30 J/ cm2晶化的薄膜结晶程度已很高     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

IGZO thin film transistors with Al2O3 gate insulators fabricated at different temperatures

Thin film transistors (TFTs) with bottom gate and staggered electrodes using atomic layer deposited Al₂O₃ as gate insulator and radio frequency sputtered In–Ga–Zn Oxide (IGZO) as channel layer are fabricated in this work. The performances of IGZO TFTs with different deposition temperature of Al₂O₃ are investigated and compared. The experiment results show that the Al₂O₃ deposition temperature play an important role in the field effect mobility, I_on/I_off ratio, sub-threshold swing and bias stability of the devices. The TFT with a 250 °C Al₂O₃ gate insulator shows the best performance; specifically, field effect mobility of 6.3 cm²/Vs, threshold voltage of 5.1 V, I_on/I_off ratio of 4×10⁷, and sub-threshold swing of 0.56 V/dec. The 250 °C Al₂O₃ insulator based device also shows a substantially smaller threshold voltage shift of 1.5 V after a 10 V gate voltage is stressed for 1 h, while the value for the 200, 300 and 350 °C Al₂O₃ insulator based devices are 2.3, 2.6, and 1.64 V, respectively.     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.     

Pentacene thin film transistors fabricated by solution process with directional crystal growth

We have fabricated solution-processed pentacene thin film transistor arrays with mobilities as high as 1.0 cm²/V s, evaluated at a low drain voltage of ?10 V. This is achieved by controlling the growth direction of the pentacene films from solution, and by optimizing conditions for drop casting. Crystal growth of the solution-processed pentacene films is found to proceed in one direction on a tilted substrate. Grazing incidence X-ray diffraction and electron diffraction reveal that the crystal growth azimuth corresponds to the direction along the minor axis of the a–b plane in the unit cell of the pentacene crystal. This directional growth method is extended to solution processing on large glass substrates with an area of 150 × 150 mm², thereby yielding transistor arrays with two-dimensional uniformity and high carrier mobility.     

Planarization of amorphous silicon thin film transistors by liquidphase deposition of silicon dioxide

A planarized device structure was developed for amorphous silicon thin film transistors to overcome the gate leakage problem. Utilizing the liquid phase deposition technique, a silicon oxide film with thickness exactly equal to the gate height was grown around the gate to planarize the surface for the fabrication of inverted staggered thin film transistors. The planarized thin film transistor has smaller leakage current and better performance, i.e., field effect mobility, subthreshold swing, etc. This novel process has a potential to improve the yield of large area liquid crystal display     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Optimization of nanocomposite gate insulators for organic thin film transistors

Nanocomposite gate insulators consisting of (Ba, Sr)TiO₃ (barium strontium titanate; BST) nanoparticles and crosslinked poly(4-vinyl phenol) (PVP) polymers were fabricated. Well-dispersed nanocomposite films were prepared by optimizing the BST nanoparticle size sorting process (ultrasound crushing and centrifuge method). The size-sorted BST nanoparticles (∼30 nm in size) were homogeneously mixed in the PVP host polymer in various BST contents, from 0 to 70 wt%, to tune the dielectric constant (κ) of the resulting nanocomposite films. The composite films exhibit three-fold increase in the κ value from 3.9 to 11.3. The physical properties including leakage current and surface roughness of the composites were also measured as a function of the BST loading content and particle dispersion. The relationship between these properties and the electrical performance of the corresponding organic thin film transistor were explored.     

Starch as ion-based gate dielectric for oxide thin film transistors

Application of nature bio-materials in electronics represents an emerging field of science and technology that began a few years ago. For the dielectric of transistors, the ion-based electric double layer (EDL) gating has becoming the widely accepted theory of charge modulation with hydrated bio-polymer dielectrics. Herein, we report on the use of starch as the ion-based gate dielectric for oxide thin film transistors. Two types of starches, i.e., water-soluble starch and potato starch were studied either with or without the incorporation of glycerol. Important parameters including mechanical strength, surface morphology, specific capacitance and ion conductivity were analyzed in accordance with the molecular structure of starches. The transistor performance was found in close relation with the specific capacitance and ion conductivity of the starch dielectrics. Higher on/off ratio (2.6 × 10⁶) and field mobility (0.83 cm²V⁻¹s⁻¹) were obtained with glycerol incorporated potato starch due to the advantage in capacitance and ion conductivity. Lower ion conductivity of the water-soluble starch on the other hand caused the large current hysteresis, so the current retention property was examined for the potential application as a memory element. Collectively, this work solidifies our knowledge on the material type, EDL gating mechanism and applicability of nature bio-material gated transistors.     

Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm²/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 10⁵ and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

Low-voltage organic thin film transistors with hydrophobic aluminum nitride film as gate insulator

This paper reports on the low-voltage (<5 V) pentacene-based organic thin film transistors (OTFTs) with a hydrophobic aluminum nitride (AlN) gate-dielectric. In this work, a thin (about 50 nm), smooth (roughness about 0.18 nm) and low-leakage AlN gate dielectric is obtained and characterized. The AlN film is hydrophobic and the surface free energy is similar to the organic or the polymer films. The demonstrated AlN–OTFTs were operated at a low-voltage (3–5 V). A low-threshold voltage (−2 V) and an extremely low-subthreshold swing (∼170 mV/dec) were also obtained. Under low-voltage operating conditions, the on/off current ratio exceeded 10⁶, and the field effect mobility was mobility was 1.67 cm²/V s.     

Rapid thermal oxidation of silicon for thin gate dielectric

Rapid thermal oxidation of silicon has been carried out in the temperature range 1000 to 1250°C for an oxidation time of 5 to 60 s. The new kinetics data show that oxidation is carried out by a two-energy activation process. Assuming linear growth during the first 5 s of fast oxidation, the first process occurs with an activation energy Ea of 0.9 eV. The second process takes place with Ea = 1.4 eV for linear growth kinetics from 5 to 60 s.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V