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1.
The Gm-C technique is extensively used for continuous-time filtering applications because it results in tunable, wideband and compact designs. In this paper, an OTA architecture using a novel bulk-input differential pair without the use of a tail current source is proposed. Good CMRR is still achieved by using the gate terminal to control the total current in the differential pair, via the use of a dummy pair. The OTA also exhibits a wide differential input range and good Gm-tunability. For this design, two standard double-poly double-metal CMOS processes were investigated: a 0.8 m process having a nominal threshold voltage of around 0.7 V and a 0.35 m process having a nominal threshold voltage of 0.5 V. Simulation results are presented for both designs while test results are presented, for the OTA, implemented using the 0.8 m process, used in a second order cochlea low-pass filter.Ivan Grech received his B.Eng.(Hons.) degree in 1993 and M.Sc. in 1996 from the University of Malta. In 1994 he joined the Department of Microelectronics at the University of Malta where he is employed as a lecturer. He received the Ph.D. degree from the University of Surrey, U.K. in 2002. His research interest is in CMOS analog integrated circuit design.Joseph Micallef received his B.Sc. Eng(Hons.) degree in electronics engineering from the University of Malta in 1972, and M.Sc. and Ph.D. degrees in electrical engineering from the University of Surrey, U.K., in 1989 and 1993, respectively. From 1973 to 1981, he was with General Instruments, engaged in work on high voltage components and circuits and on IFTs. He moved to SGS-THOMSON Microelectronics in 1981 where he was involved with packaging of MOS ICs. In 1989, he joined the Faculty of Engineering at the University of Malta and is now lecturer in the Department of Microelectronics. His current research activities include analog integrated circuit design, as well as optical properties of III-V quantum well structures.George Azzopardi photo/biography not available upon publication.Carl J. Debono photo/biography not available upon publication. 相似文献
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G. Ferri M. Faccio G. Stochino A. D'Amico D. Rossi G. Ricotti 《Analog Integrated Circuits and Signal Processing》1999,20(1):11-23
A new bipolar four-quadrant operational amplifier operating at a power supply voltage of 0.8 V and with a supply current of 800 A is here presented and illustrated. It features low input offset, low bias current, low noise, low crossover distortion and a rail-to-rail output swing. Control circuits ensuring minimum and maximum current limits for the output transistors have been incorporated. The biasing circuitry follows a PTAT scheme. A simple compensation topology allows the reduction of the area. The chip, whose area is about 2 mm2, has been fabricated in HF2CMOS 2 /6 GHz technology. Finally, Spice simulations and experimental results, which confirm the expected overall performances of the low voltage op-amp, are reported. 相似文献
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介绍了一种50 MHz,10位,5V流水线模数转换器的设计.为实现低功耗设计目标,将比较器和OTA作为主要优化对象,采用改进的动态比较结构和套筒式余量放大器(OTA)分别实现上述功能.本设计在0.5μm CMOS工艺下实现,工作在50 MHz条件下功耗为190 mW. 相似文献
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提出了一种静态功耗很低的BICMOS LD0线性集成稳压器的实现方法,详细分析了它的工作原理,并给出了具体电路、仿真波形以及分析数据。该电路的主要特点是采用一种自偏置电流基准源,有很强的电源抑制比和很好的温度特性。高电流效率的输出缓冲器,用以降低电路的静态功耗。为防止输出电压过冲,采用误差放大器与NMOS管的结构进行调节,这样保证了输出电压在输入电压上电的过程中无过冲。 相似文献
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设计了一种低功耗曲率补偿带隙基准电压源。利用亚阈值MOS管差分对,产生曲率补偿电流,对输出基准电压进行曲率补偿。采用低功耗运放来增强基准电压源的电源抑制能力,同时降低基准电压源的功耗。采用SMIC 0.18 μm 混合信号CMOS工艺进行设计。仿真结果表明,在1.5 V电源电压下,基准电压源的输出基准电压为1.224 V,在-40 ℃~125 ℃范围内的温度系数为1.440×10-6/℃~4.076×10-6/℃,电源抑制比为-77.58 dB,消耗电流为225.54 nA。 相似文献
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设计了一种低功耗、宽电源电压范围的电机驱动器。通过采用高效率泵电路,设计新型的电荷泵供电方式,使得电机驱动电路能够实现宽电源电压范围和低功耗。该驱动器保证功率管在低压下仍具有较低的导通电阻和较大的输出驱动电流,而在高压情况下功率管栅源不会被击穿。设计电荷泵时钟控制电路,使得驱动器具有更低的功耗。基于SMIC 180 nm BCD工艺完成设计。仿真结果表明,该电机驱动器的电机电源输入范围为0~15 V,逻辑电源范围为1.8~5.5 V,且静态功耗为284.5μA。 相似文献
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提出了一种低压低功耗有源电感(LVLPAI)。它由新型正跨导器、负跨导器以及电平转换模块构成。其中,电平转换模块与新型正跨导器的输入端和负跨导器的输出端连接,同时,新型正跨导器采用了PMOS晶体管,并将栅极和衬底短接,最终使得有源电感可在低压下工作,且在不同频率下具有低的功耗。基于0.18 μm RF CMOS工艺进行性能验证,并与传统AI进行对比。结果表明,LVLPAI和传统AI比较,在1.5 GHz、2.7 GHz、4.4 GHz这三个频率处分别取得三个电感值3 326 nH、1 403 nH、782 nH的条件下,前者和后者的工作电压分别为0.8 V、1 V、1.2 V和1.5 V、1.6 V和1.7 V,分别下降了46.7%、37.5%、29.4%;功耗分别为0.08 mW、0.25 mW、0.53 mW和0.14 mW、0.31 mW、0.62 mW,分别下降了42.9%、19.4%、14.5%。 相似文献
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设计了一种超低功耗、无片上电阻、无双极型晶体管的基于CMOS亚阈值特性的基准电压源。采用Oguey电流源结构来减小静态电流,从而降低功耗,并加入工作于亚阈值区的运算放大器,在保证低功耗的前提下,显著提高了电源电压抑制比。采用1.8 V MOS管与3.3 V MOS管的阈值电压差进行温度补偿,使得输出电压具有超低温度系数。采用共源共栅电流镜以提高电源电压抑制比和电压调整率。电路基于SMIC 0.18 μm CMOS工艺进行设计和仿真。仿真结果表明,在-30 ℃~125 ℃温度范围内,温漂系数为9.3×10-6/℃;电源电压为0.8~3.3 V时,电压调整率为0.16%,电源电压抑制比为-58.2 dB@100 Hz,电路功耗仅为109 nW,芯片面积为0.01 mm2。 相似文献
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设计了一款用于实现10位精度逐次逼近型模数转换器(SAR ADC)的电压比较器,该比较器采用高速高精度比较器结构并进行了优化,在高速度、低功耗锁存器的基础上加预放大级以提高比较精度,加RS触发器优化处理比较器的输出信号。同时,采用失调校准技术消除失调,预放大级采用共源共栅结构抑制回程噪声,最终获得了高精度和较低的功耗。仿真结果表明:在Chartered 0.35μm 2P4MCMOS工艺下,时钟频率5 MHz,电源电压3.3 V,分辨率达0.1 mV,平均功耗约为0.45 mW,芯片测试结果表明比较器满足了SAR ADC的要求。 相似文献
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提出了一种基于1553B总线的收发器系统结构,设计实现了低压单电源供电的1553B总线收发器,有效降低了收发器的动态功耗。仿真及测试结果表明,该电路能在3.3 V的低电压下实现所有的收发功能,总线占空比为100%时的最大动态功耗仅为0.5 W,相比于5 V供电的1553B总线收发器,其动态功耗大约下降了1.7 W。该收发器采用0.5μm DPTM BCD (15 V)工艺流片,并已成功应用到低压的1553B总线产品中。 相似文献
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An analog frontend block of a VLSI readout chip, dedicated to high spatial resolution X or beta ray imaging, using capacitive silicon detectors, is described. In the present prototype, an ENC noise of 343 electrons at 0 pF with a noise slope of 28 electrons/pF has been obtained for a peaking time of 10 s, a 37 mV/fC conversion gain, a 3.5 V power supply and a 150 W/channel power consumption. 相似文献
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Changku Hwang Akira Hyogo Hong-sun Kim Mohammed Ismail Keitaro Sekine 《Analog Integrated Circuits and Signal Processing》2000,25(3):347-350
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V
t
|+2 V
ds,sat
and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 m N-well process with a 3 V supply are given. 相似文献
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低压、低功耗SOI电路的进展 总被引:3,自引:1,他引:2
最近 IBM公司在利用 SOI(Silicon- on- insulator)技术制作计算机中央处理器 (CPU)方面取得了突破性的进展 ,该消息轰动了全世界。SOI电路最突出的优点是能够实现低驱动电压、低功耗。文中介绍了市场对低压、低功耗电路的需求 ,分析了 SOI低压、低功耗电路的工作原理 ,综述了当前国际上 SOI低压、低功耗电路的发展现状。 相似文献
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设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12. 相似文献
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设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12. 相似文献
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提出了一种全MOS管结构的低压低功耗电压基准源,他利用一个工作在亚阈值区的MOS管具有负温度特性的栅-源电压与一对工作在亚阈值区的MOS管所产生的具有正温度特性的电压差进行补偿.电路采用标准的0.6 μmCMOS工艺设计,已成功应用于一个低压差线性稳压器(LDO)中,具有优良的温度稳定性,在-40~ 120 ℃范围内能达到37.4 ppm/℃,并可以在供电电压为1.4~5.5 V下工作,其总电流仅为4 μA. 相似文献
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一种低电压的Sigma-Delta ADC新结构 总被引:1,自引:1,他引:0
介绍了一种低电压Sigma-Delta ADC新结构,该结构采用了二阶单位增益ΣΔ调制器和一阶传统ΣΔ调制器相结合的方式,既可以从系统级降低对运放直流增益等非理想因素的要求,又可以减少加法器的个数、降低电路的复杂度。在此基础上,采用HJTC0.18μm1.8V/3.3V1P6M混合信号工艺,实现了一种1V工作电压的ΣΔ调制器,经测试动态范围可以达到69.5dB。 相似文献