基于SOC的低功耗管理模块设计

功耗是片上系统(SOC)设计中的关键指标之一。对于SOC芯片的低功耗设计,可以采用多种设计方法进行优化。本文设计的低功耗管理模块是通过管理工作时钟的方式对SOC的功耗进行动态调节,能够有效地降低SOC芯片的功耗。     

SOC时代低功耗设计的研究与进展

在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向.     

可编程逻辑器件低功耗技术

为降低可编程逻辑器件设计中的功耗问题,必须从系统的微结构入手,采用低功耗方案降低系统的功耗。首先介绍功耗产生的原因,并通过门控技术、器件选择、寄存器传输级的优化转换和门级低功耗优化技术4个方面,阐述了如何在逻辑层面上进行低功耗设计的基本思想和主要技术。     

基于AT91SAM7L的极低功耗系统设计

影响系统功耗的主要因素 对于一个数字系统而言,其功耗大致满足以下公式:P=CV2f,其中C为系统的负载电容,V为电源电压,f为系统工作频率.由此可见,功耗与电源电压的平方成正比,因此电源电压对系统的功耗影响最大,其次是工作频率,再就是负载电容.负载电容对设计人员而言,一般是不可控的,因此设计一个低功耗系统,应该考虑在不影响系统性能的前提下,尽可能地降低电源的电压和使用低频率的时钟.     

低功耗CMOS逻辑电路设计综述

分析了ＣＭＯＳ逻辑电路的功耗来源从降低电源电压、减 上负载电容和逻辑电路开关活动几率等方面论述了降国耗的途径。讨论了深亚微米器件中亚同值电流对功耗的影响以及减小亚阈值电流的措施,最后分析了高层次设计对降低功耗的关键作用,说明低功耗设计必须从设计的各个层次加在考虑,实现整体优化设计。     

超深亚微米数字电路的低功耗设计

随着集成电路逻辑复杂度日益提高,而工艺尺寸进入了超深亚微米数量级,低功耗设计已经成为整个SOC设计中关键的问题之一.电源电压是影响功耗的最重要因素,而阈值电压、体偏压和时钟频率也对功耗有影响.目前,对于数字电路,已经研发出一些有效地进行功耗管理,降低功耗的技术,并已应用于具体项目中.本文首先综述性地介绍几种低功耗设计方法,包括:多阈值电压CMOS技术;多电源电压;门控时钟;动态电压频率调制;动态体偏压调制;加入电源门控、以及状态可保持的电源门控技术,并逐一讨论了它们对降低功耗的具体作用.最后,针对最新的基于通用功耗格式的状态保持电源门控技术,本文概述其实现步骤.     

一种基于电压窗口技术的超低功耗SAR ADC

本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及l0kS/s的采样频率下,ADC的信噪失真比(SNDR)为73.3dB,总功耗为432nW,品质因数(FOM)为11.4fJ/Conv.     

采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

通用视频输出控制器IP核的低功耗设计

随着芯片的集成度越来越高,芯片的功耗成为芯片设计中越来越重要的优化参数。设计了一种可应用于视频处理芯片、多媒体手持设备、嵌入式SoC等系统中的视频输出控制器。设计中通过多种工艺无关的低功耗设计技术优化控制器的动态功耗。首先分析各子模块的工作频率,降低低速子模块的工作时钟,然后通过添加门控时钟单元降低时钟的翻转次数。应用Design Compiler[1]进行工程的功耗分析,结果表明设计中使用的低功耗设计方法有效降低了模块的动态功耗。     

采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

低功耗方法在SoC芯片设计中的应用

SOC芯片设计在集成电路设计中占据重要位置,低功耗设计是SoC设计过程中的重要环节。本文首先全面分析了CMOS电路的功耗组成和功耗估计的相关理论,随后从各个设计层次详细分析了SOC芯片低功耗设计的理论及其实现方法。     

Low-power design for embedded processors

Minimization of power consumption in portable and battery powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made in implementation of the architecture     

Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application

This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high V_th for good standby power and low V_th for high speed. Based on this optimization technique using two cell libraries with different threshold voltages, a 16-bit multiplier using the dual-threshold cells meeting the speed requirement has been designed to have a 50% less leakage power consumption when compared to the one using only the low-threshold cell library.     

Zigbee芯片低功耗测试平台研究

文章针对具有Zigbee收发模块的SOC芯片,设计了低功耗实验平台,以纽扣电池为供电电源,研究其在低功耗环境下的耗电情况。通过设置芯片的多种工作模式来模拟真实工作状态,以不同的测量方式来使数据更加全面准确。使用实验数据分析了Zigbee网络节点的低功耗性能,得到了具有一定参考价值的低功耗设计方法。     

CMOS VCO's for PLL frequency synthesis in GHz digital mobile radiocommunications

CMOS inductorless voltage controlled oscillator (VCO) design is discussed with the emphasis on low-noise, low-power, gigahertz-range circuits suitable for portable wireless equipment. The paper considers three VCO structures-one simple ring oscillator and two differential circuits. The design methodology followed optimization for high-speed and low-power consumption. The proposed linearized MOSFET model allows the accurate prediction of the operating frequency while the phase noise evaluation technique makes it possible to determine, through simulation, the relative phase-noise performance of different oscillator architectures. The measurement results of three VCO's implemented in 1.2-μm CMOS technology confirm with the simulation predictions. The prototype VCO's exhibits 926-MHz operation with -83 dBc/Hz phase noise (@ 100 kHz carrier offset) and 5 mW (5 V) power consumption     

低功耗无线收发电路系统设计

目前,无线通信技术发展极其迅速,随之引起系统功耗不断上升。因此人们近几年来对无线通信网络中各方面的低功耗技术进行了深入的研究,使节能成为无线通信发展的一个重要方向。设计了低功耗无线收发电路系统,采用STM32L151系列超低功耗芯片和UTC4432系列无线通信模块作为核心电路系统,通过软件设计及调试实现整个低功耗收发电路系统功能。结果表明:采用合适的微控制器和无线通信模块对于控制无线收发电路系统的功耗有着极其重要的作用,再加上对软件编程的控制,能够使整个系统的功耗大幅度降低。     

Guest Editorial Special Section on Low-Power Electronics and Design

The eight papers in this special section were published in the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), held in Tegernsee, Germany, October 4-6, 2006. The papers cover various areas related to low-power electronics and design, ranging from circuit and design technology to system level power modeling and optimization. The papers are summarized here.     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

手持式电子测量系统的低功耗没计

目前,电池供电的手持式电子测量仪器应用越来越广泛,各种测量仪器都出现了手持式的型号。这给电子设计工程师在系统功耗设计上带来了新的挑战。文中就低功耗系统设计的原则进行了分析,提出了从器件选择,供电效率,系统总体设计等方面来降低功耗的方法。