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1.
Dependence of ionization current on gate bias in GaAs MESFETs 总被引:1,自引:0,他引:1
Canali C. Neviani A. Tedesco C. Zanoni E. Centronio A. Lanzieri C. 《Electron Devices, IEEE Transactions on》1993,40(3):498-501
The nonmonotonic behavior of gate current I g as a function of gate-to-source voltage V gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I g(V gs) curve is strongly related to the drop of the electric field in the channel of the device as V gs is moved towards positive values 相似文献
2.
A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I g-V g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I g- V g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I g-V g measurements 相似文献
3.
A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (gm) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V gs). That is, the electrons mainly drift in a highly doped channel region at a shallow V gs. A plateau g m region and the maximum g m were achieved at a V gs range of -0.25~+0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I ds) region and nearly equal in the middle and high I ds region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry 相似文献
4.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献
5.
A method of obtaining the spatial distribution of hot-carrier-induced trapped electrons in the gate oxide (N 0t(x )) of PMOSFETs is introduced with the aid of a two-dimensional simulator. The measured I ds versus V ds for various V gs for low drain bias and I ds versus V gs have been compared with data obtained from the simulation concerning the obtained spatial distribution of trapped electrons in the gate oxide. There exists a high degree of agreement between the measured current-voltage characteristics after hot-carrier stress and the simulation results concerning the newly obtained spatial distribution of trapped electrons in the gate oxide 相似文献
6.
Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I sub condition (V g =0.5 V d). However, in the high-gate-bias region (V g=V d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V g>V d), this current-crowding effect in the diagonal transistor can be a serious reliability concern 相似文献
7.
The effects of traps in GaAs MESFETs are studied using a pulsed gate measurement system. The devices are pulsed into the active region for a short period (typically 1 μs) and are held in the cutoff region for the rest of a 1-ms period. While the devices are on, the drain current is sampled and a series of pulsed gate I -V curves are obtained. The drain current obtained under the pulsed gate conditions for a given V GS and V DS gives a better representation of the instantaneous current for a corresponding V gs and V ds in the microwave cycle because of the effects of traps. The static and pulsed gate curves were used in a nonlinear time-domain model to predict harmonic current. The results showed that analysis using pulsed gate curves yielded better predictions of harmonic distortion than analysis based on conventional state I -V curves under large-signal conditions 相似文献
8.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
9.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
10.
Vuillaume D. Marchetaux J.-C. Lippens P.-E. Bravaix A. Boudou A. 《Electron Devices, IEEE Transactions on》1993,40(4):773-781
The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V d/8 to V d) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I d-V g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-V g degradation 相似文献
11.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
12.
Busta H.H. Zimmerman B.J. Tringides M.C. Spindt C.A. 《Electron Devices, IEEE Transactions on》1991,38(11):2558-2562
A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current I FN. Based on these observations, a simple model has been developed to calculate the I -V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from I c=I FN-I g as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated 相似文献
13.
The authors report on the off-state gate current (I g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I g at drain voltages as low as 4 V and an I g injection efficiency reaching 0.8, as compared to 8.5 V and 10-7 in SiO2 devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure 相似文献
14.
Laskar J. Ketterson A.A. Baillargeon J.N. Brock T. Adesida I. Cheng K.Y. Kolodzey J. 《Electron Device Letters, IEEE》1989,10(12):528-530
The observation of negative differential resistance (NDR) and negative transconductance at high drain and gate fields in depletion-mode AlGaAs/InGaAs/GaAs MODFETs with gate lengths L g ~0.25 μm is discussed. It is shown that under high bias voltage conditions, V ds>2.5 V and V gs>0 V, the device drain current characteristic switches from a high current state to a low current state, resulting in reflection gain in the drain circuit of the MODFET. The decrease in the drain current of the device corresponds to a sudden increase in the gate current. It is shown that the device can be operated in two regions: (1) standard MODFET operation for V gs<0 V resulting in f max values of >120 GHz, and (2) a NDR region which yields operation as a reflection gain amplifier for V gs >0 V and V ds>2.5 V, resulting in 2 dB of reflection gain at 26.5 GHz. The NDR is attributed to the redistribution of charge and voltage in the channel caused by electrons crossing the heterobarrier under high-field conditions. The NDR gain regime, which is controllable by gate and drain voltages, is a new operating mode for MODFETs under high bias conditions 相似文献
15.
It is reported that fluorine can jeopardize p+-gate devices under moderate annealing temperatures. MOSFETs with BF2 or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 12 cm-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I -V characteristics of PMOSFET with fluorine incorporated p+-gate revealed that the long gate-length device had abnormal abrupt turn-on I d-V g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I d-V g characteristics associated with long-gate-length p+-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C -V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p+-gate devices is presented. The incorporation of fluorine in the p+ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states 相似文献
16.
A simple method is proposed for extracting the electrical parameters of a silicon-on-insulator (SOI) material from a depletion-mode MOSFET. It is based on an analysis of static input current-voltage I D(V G) and transconductance-voltage g m(V G) characteristics in the linear region. Functions varying linearly with gate voltage are constructed from I D(V G) and g m(V G) functions. These new functions allow a straightforward determination of the parameters usually obtained from a capacitance-voltage measurement (doping level, oxide charge, etc.) and also the bulk-layer and accumulation-layer carrier mobility 相似文献
17.
Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N2O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N2O oxide has significant improvement in t BD (2×under-V g unipolar stress, 20×under+V g unipolar stress, and 10×under bipolar stress). The improvement of t BD in N2O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO2/Si interface 相似文献
18.
Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I d-V gs characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO2 interface. It is shown that damage from low drain current stress occurs at the Si-SiO2 interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO2 interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO2 interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO2 interface at the drain junction edge 相似文献
19.
A simplified analytical expression for the temperature dependent saturated I D-V D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I D versus V G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I D and more severe gate voltage hysteresis characteristics 相似文献
20.
Magneto-transport and cyclotron resonance measurements were made to determine directly the density, mobility, and the effective mass of the charge carriers in a high-performance 0.15-μm gate In0.52 Al0.48As/In0.53Ga0.47As high-electron-mobility transistor (HEMT) at low temperatures. At the gate voltage V G=0 V, the carrier density n g under the gate is 9×1011 cm-2, while outside of the gate region n g=2.1×1012 cm-2. The mobility under the gate at 4.2 K is as low as 400 cm2/V-s when V G<0.1 V and rapidly approaches 11000 cm2/V-s when V G>0.1 V. The existence of this high mobility threshold is crucial to the operation of the device and sets its high-performance region in V G>0.1 V 相似文献