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1.
A 900-MHz 1.5-V CMOS voltage-controlled oscillator using switched resonators with a wide tuning range 总被引:3,自引:0,他引:3
A 900-MHz fully integrated VCO was fabricated in a 0.18-/spl mu/m foundry CMOS process. Under 1.5 V power supply, this VCO can be tuned from 667 MHz to 1156 MHz which corresponds to a 53.6% tuning range. The VCO has nearly constant phase noise over the whole tuning frequency, credit to the switched resonators used in this VCO. The phase noise at a 600 kHz offset is -123.1 dBc/Hz at 1125 MHz center frequency and -124.2 dBc/Hz at 667 MHz center frequency. 相似文献
2.
A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption. 相似文献
3.
Nam-Jin Oh Sang-Gug Lee 《Microwave and Wireless Components Letters, IEEE》2005,15(11):736-738
This paper presents current reused voltage controlled oscillator (VCO) topologies by stacking switching transistors in series like a cascode. The VCOs can operate with only half the amount of dc current compared to those of the conventional VCO topologies. Fabricated in 0.18-/spl mu/m CMOS process, a differential VCO operates in a 2.1-GHz band with a phase noise of -110dBc/Hz at 1-MHz offset, and a quadrature VCO operates in a 3.1-GHz band with a phase noise of -102dBc/Hz at 1-MHz offset. The proposed topologies can be adopted for low-power applications. 相似文献
4.
A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop 总被引:2,自引:0,他引:2
A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V. 相似文献
5.
A balanced Colpitts voltage-controlled oscillator (VCO) is designed and fabricated in a commercially available 0.25-/spl mu/m SiGe BiCMOS process. It has the characteristics of the push-push VCO, i.e., the VCO has simultaneously a differential output at a fundamental frequency of 21.5 GHz and a single-ended output at the second harmonic frequency of 43 GHz. A differential tuning technique is applied to reduce the phase noise. The measured phase noise at 1-MHz offset is -113 dBc/Hz at 21.5 GHz and -107 dBc/Hz at 43 GHz. The corresponding output power is about -6 and -17 dBm, respectively, with a 5% tuning range and a 130-mW dc power consumption. 相似文献
6.
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology 总被引:1,自引:0,他引:1
Neric Fong Jonghae Kim Plouchart J.-O. Zamdmer N. Duixian Liu Wagner L. Plett C. Tarr G. 《Solid-State Circuits, IEEE Journal of》2004,39(5):841-846
The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads). 相似文献
7.
A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/. 相似文献
8.
Low phase noise IP VCO for multistandard communication using a 0.35-/spl mu/m BiCMOS SiGe technology
Coustou A. Dubuc D. Graffeuil J. Llopis O. Tournier E. Plana R. 《Microwave and Wireless Components Letters, IEEE》2005,15(2):71-73
In this letter, we report that a commonly used 0.35-/spl mu/m, 60-GHz-F/sub MAX/ BiCMOS SiGe monolithic microwave integrated circuit (MMIC) technology is able to provide very low phase noise signal generation in the X-band frequency range. This statement has been demonstrated using a differential LC voltage-controlled oscillator (VCO) in which varactors are realized with metal-oxide semiconductor (MOS) transistors and inductors with a patterned ground shield technology. This VCO features an output power signal in the range of -5 dBm and exhibits a phase noise of -96 dBc/Hz at a frequency offset of 100kHz from carrier and -120 dBc/Hz at a frequency offset of 1 MHz. The VCO features a tuning range of 430 MHz or 4.3% of its operating frequency. Its power consumption is in the range of 70 mW (200 mW with buffers circuits) for a chip size of 800/spl times/1000 /spl mu/m/sup 2/ (including RF probe pads). 相似文献
9.
Zhan J.-H.C. Duster J.S. Kornegay K.T. 《Microwave and Wireless Components Letters, IEEE》2005,15(3):156-158
A 37-GHz voltage controlled oscillator (VCO) fabricated in IBM's 47-GHz SiGe BiCMOS technology is presented. The VCO achieves a phase noise of -81dBc/Hz at 1-MHz offset from the carrier while delivering an output power of -30dBm to 50 /spl Omega/ buffers. Drawing 15-mA of dc current from a 3-V power supply the VCO occupies 350/spl mu/m/spl times/280/spl mu/m of silicon area. Capacitive emitter degeneration and compact layout are used to achieve high f/sub OSC//f/sub T/ ratio. 相似文献
10.
Hyungki Huh Yido Koo Kang-Yoon Lee Yeonkyeong Ok Sungho Lee Daehyun Kwon Jeongwoo Lee Joonbae Park Kyeongho Lee Deog-Kyoon Jeong Kim W. 《Solid-State Circuits, IEEE Journal of》2005,40(11):2228-2236
The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-/spl mu/m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a /spl Delta//spl Sigma/ modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc. 相似文献
11.
Chun-Huat Heng Bang-Sup Song 《Solid-State Circuits, IEEE Journal of》2003,38(6):848-854
A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm. 相似文献
12.
A 5-GHz low phase noise differential colpitts CMOS VCO 总被引:1,自引:0,他引:1
Ming-Da Tsai Yi-Hsien Cho Huei Wang 《Microwave and Wireless Components Letters, IEEE》2005,15(5):327-329
A low noise 5-GHz differential Colpitts CMOS voltage-controlled oscillator (VCO) is proposed in this letter. The Colpitts VCO core adopts only PMOS in a 0.18-/spl mu/m CMOS technology to achieve a better phase noise performance since PMOS has lower 1/f noise than NMOS. The VCO operates from 4.61 to 5 GHz with 8.3% tuning range. The measured phase noise at 1-MHz offset is -120.42 dBc/Hz at 5 GHz and -120.99 dBc/Hz at 4.61 GHz. The power consumption of the VCO core is only 3 mW. To the authors' knowledge, this differential Colpitts CMOS VCO achieves the best figure of merit (FOM) of 189.6 dB at 5-GHz band. 相似文献
13.
A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-/spl mu/m CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 /spl mu/W and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage. 相似文献
14.
Han-il Lee Je-Kwang Cho Kun-Seok Lee In-Chul Hwang Tae-Won Ahn Kyung-Suc Nah Byeong-Ha Park 《Solid-State Circuits, IEEE Journal of》2004,39(7):1164-1169
A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications. 相似文献
15.
Yi-jan Emery Chen Wei-Min Lance Kuo Zhenrong Jin Jongsoo Lee Tretiakov Y.V. Cressler J.D. Laskar J. Freeman G. 《Microwave Theory and Techniques》2005,53(5):1672-1681
An integrated low-power low phase-noise Ka-band differential voltage-controlled oscillator (VCO) is developed in a 0.12-/spl mu/m 200-GHz silicon-germanium heterojunction bipolar transistor technology. The use of line inductors instead of transmission lines is demonstrated to be feasible in LC-tuned resonators for Ka-band applications. This VCO can operate from a supply voltage of 1.6-2.5 V. A single-sideband phase noise of -99 dBc/Hz at 1-MHz offset from the carrier frequency of 33 GHz is achieved, together with a VCO figure-of-merit of -183.7 dBc/Hz. The frequency tuning constant of the VCO in the linear regime is -0.547 GHz/V. 相似文献
16.
The impact of device type and sizing on phase noise mechanisms 总被引:7,自引:0,他引:7
Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process. 相似文献
17.
A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW. 相似文献
18.
Nam-Jin Oh Sang-Gug Lee 《Microwave and Wireless Components Letters, IEEE》2005,15(11):733-735
A fully integrated back-gate transformer feedback CMOS differential voltage-controlled oscillator (VCO) has been designed for high-frequency and low-phase noise operation using an 0.18-/spl mu/m CMOS process. The proposed VCO topology utilizes the monolithic transformer feedback configuration from the drain to the back-gate of the switching transistors in VCO. The VCO operating in an 11-GHz band shows the phase noise of -109dBc/Hz at 1-MHz offset, and draws around 3.8mA in the differential core circuits from a 1.8-V power supply. 相似文献
19.
A low phase-noise CMOS VCO with harmonic tuned LC tank 总被引:2,自引:0,他引:2
Huijung Kim Seonghan Ryu Yujin Chung Jinsung Choi Bumman Kim 《Microwave Theory and Techniques》2006,54(7):2917-2924
This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped voltage at the switching differential cell, which effectively maximizes the slope of the switching cell output voltage at a zero crossing point. In addition, the proposed technique also suppresses the down-conversion of the noise around the second harmonic frequency by the second harmonic short of the tank. One second HT VCO and two third HT VCOs are designed and implemented to evaluate the concept using a 0.35- and 0.13-/spl mu/m CMOS process. The figure-of-merit (FOM) of the second HT VCO, third HT VCO1, and third HT VCO2 are -180.7, -183.7, and -189.5, respectively. The best FOM performance of the VCO has phase noises of -100.4, -132.0, and -140.8dBc/Hz at 100-kHz, 1-MHz, and 3-MHz offset frequencies at the 2-GHz carrier, respectively. This VCO consumes 3.29 mA from a 1.8-V supply with the silicon area of 500 /spl mu/m/spl times/750 /spl mu/m. 相似文献
20.
A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 0.13 /spl mu/m CMOS logic process. The VCO can be tuned from 191.4 to 192.7 GHz. The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 1.5 V supply. 相似文献