Quadruply Self-Aligned MOS (QSA MOS) -- A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

Polysilicon oxidation self-aligned MOS (POSA MOS) — A new self-aligned double source/drain ion implantation technique for VLSI

A new MOS device named polysilicon oxidation self-aligned (POSA) MOS is proposed to enhance device performance for VLSI circuits. The device characteristics revealed significant improvement in hot-electron effects, short-channel effects and punch through voltage.     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n⁺and p⁺junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n⁺and p⁺junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils²feasible with 1-µm design rules, is also discussed.     

Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memory

A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta2O5capacitor stacked on it. By this cell, the ultimate cell area3F times 2Fcan be realized with sufficient operating margin. Here,Fis the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta2O5film was small enough for the storage capacitor dielectric. Using a3F times 4Fcell and a4Fpitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm², and a chip size of 9.2 × 9.5 mm²were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.     

RECIPE—A two-dimensional VLSI process modeling program

REnsselaer Computer integrated Circuits Process Engineering (RECIPE) is a two-dimensional (2-D) integrated circuit process modeling program developed for use in VLSI applications. The program incorporates a 2-D diffusion model which includes the concentration dependence of the diffusion coefficients. An incremental solution method is used to compute the appropriate diffusion coefficients as a function of impurity concentration throughout space. RECIPE also incorporates a 2-D ion-implantation model. While intended as a general-purpose modeling program, RECIPE has been used to study channel-length decrease of short-channel MOSFET's during high-temperature processing. A typical phosphorus-implanted (150 keV, 10¹⁶/cm²) 1-µm gate transistor had no channel after processing for 60 min at 1000°C, while an arsenic-implanted device had an effective channel length of ∼ 0.1 µm after similar processing.     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Stabilization of MOS structures by Boron ion implantation

Bias and temperature stress measurements have been used to study the effect of¹¹B ion implantation into MOS structures. The boron energies were selected so that the projected range of the implanted distribution was approximately equal to the device oxide thickness. Boron ion doses ranged from 10¹¹to 2 × 10¹²/cm². The bias temperature stress consisted of 10⁶V/cm applied at 300°C for 5 min. In all cases, the stability of the implanted capacitors was found to be significantly improved over the unimplanted.     

p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

A 920 gate DSA MOS masterslice

A DSA MOS (diffusion self-aligned MOS) masterslice circuit with up to 920 gates and a delay of 3 ns per gate has been developed for random logic computer circuits, utilizing the performance and economical advantages of the LSI masterslice approach. To attain high packing density and high speed with conventional design rules, the DSA MOSFET technology has been used for the basic device. The chip comprises 50 by 16 gate cells and 116 input/output buffers. This LSI chip is two to three times better than bipolar S-TTL in packing density and is comparable in propagation delay time. As an example of an LSI device obtained through customized metallization, an 8 bit ALU is described which has an average delay time of 3 ns and a power dissipation of 3 W.     

Electrical measurement of feature sizes in MOS Si2-gate VLSI technology

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very careful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si²-gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 µm.     

Photoresponses in In2O3transparent gate MOS capacitors

In this paper electrical and photoelectronic properties of sputtered In2O3films including 5 wt % SnO2and transparent gate MOS capacitors employing this film were discussed. In order to improve the characteristics of the sputtered films and to recover the radiation damage generated during the sputtering process, high-temperature annealing of the film in nitrogen was important. In the present experiment, the best post-annealing temperature was about 850°C, and the minimum resistivity ρ and the interface-state density Nsswhich resulted from this annealing were 1.1 × 10^-3Ω . cm and 6.5 × 10¹⁰cm^-2. eV^-1, respectively. The dark current was comparable to that of conventional Al-gate MOS capacitors. Moreover, it became clear that the recombination loss of photogenerated carriers due to the interface states caused the degradation of the spectral response in the short wavelength range, when the surface of the MOS substrate was maintained in the vicinity of mid-gap potential. However, the transparent gate MOS capacitors biased in weak or strong inversion could be usable as high-sensitivity, photosensors in the blue region of the spectrum, because the interface states could not act as effective recombination centers for these bias conditions.     

n-channel MOS transistors in mercury—cadmium—telluride

n-channel MOS transistors operating at 77 K have been realized in Hg0.71Cd0.29Te with ion-implanted source and drain junctions. Enhancement-mode transistors were made with evaporated ZnS as a gate insulator, and depletion-mode transistors were made using a native oxide of mercury-cadmium-telluride. The devices exhibit surface mobility as high as 1.5 × 10⁴cm². V^-1. s^-1. Current-voltage characteristics and capacitance-voltage data are presented and analyzed.     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

A highly latchup-immune 1-µm CMOS technology fabricated with 1-MeV ion implantation and self-aligned TiSi2

A 1-µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. Important features in this technology include thin epi substrate, retrograde n-well formed by 1-MeV ion implantation, As-P graded junctions, and self-aligned titanium disilicide. The 1-µm CMOS technology has been characterized by examining the deviceI-Vcurves, avalanche-breakdown voltages, subthreshold characteristics, short-channel effect, and sheet resistances. The devices fabricated by using the 1-MeV ion implantation and self-aligned titanium disilicide do not deviate from the conventional devices constructed with the same level of technology. With the As-P double-diffused LDD structure for the n-channel device, the avalanche-breakdown voltage is increased and hot-electron reliability is greatly improved. The titanium disilicide process effectively reduces the sheet resistances of the source-drain and the polysilicon gate to 3 Ω/□ compared with 150 Ω/□ of the unsilicided counterparts. The optimized 1-µm device channel n-well CMOS resulted in a propagation delay time of 150 ps with a power dissipation of 0.3 mW. With the thin epi wafers and the retrograde n-well structure, latchup immunity is found to be greatly improved. Moreover, with the titanium disilicide formation on the source-drain, the latchup holding voltage is found to be extremely high (13 V) with the substrate grounded from the backside of the wafer. If the backside substrate is not grounded, self-aligned disilicide over n⁺and p⁺regions are found necessary to ensure high latchup immunity even in the case of thin epi on heavily doped substrate. The degradation of emitter efficiency due to the TiSi2is believed to be the dominant factor in raising the holding voltage. Detailed experimental results and discussions are presented.     

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV^-2. The bipolar transistors have a low-resistance base contact. Current gain βFcan be set independently. Forbeta_{F} = 90, the Early voltage isV_{A} = 110V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.