High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

The Electrical and Interfacial Properties of Metal-High-$kappa$ Oxide-Semiconductor Field-Effect Transistors With $hbox{LaAlO}_{3}$ Gate Dielectric

$hbox{LaAlO}_{3}$ is a promising candidate for gate dielectric of future VLSI devices. In this letter, n-channel metal–oxide–semiconductor field-effect transistors with $hbox{LaAlO}_{3}$ gate dielectric were fabricated, and the electron mobility degradation mechanisms were studied. The leakage current density is $hbox{7.6} times hbox{10}^{-5} hbox{A/cm}^{2}$ at $-!$ 1 V. The dielectric constant is 17.5. The surface-recombination velocity, the minority-carrier lifetime, and the effective capture cross section of surface states were extracted from gated-diode measurement. The rate of threshold voltage change with temperature $(Delta V_{T} / Delta T)$ from 11 K to 400 K is $-!$ 1.51 mV/K, and the electron mobility limited by surface roughness is proportional to $E_{rm eff}^{-0.66}$.      

A Center-Offset Polycrystalline-Silicon Thin-Film Transistor With ${rm n}^{+}$ Amorphous-Silicon Contacts

We have studied a bottom-gate polycrystalline-silicon thin-film transistor (poly-Si TFT) with amorphous-silicon (a-Si) ${rm n}^{+}$ contacts and center-offset gated structure, where intrinsic poly-Si is used in the center-offset region. The fabrication process is compatible with the conventional a-Si TFT with addition of thermal annealing for crystallization of a-Si. The bottom-gate poly-Si TFT with a 5-$muhbox{m}$ offset length exhibited a field-effect mobility of 18.3 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and minimum OFF-state current of $hbox{2.79} times hbox{10}^{-12} hbox{A}/muhbox{m}$ at $V_{rm ds} = hbox{5} hbox{V}$. The leakage currents are two orders of magnitude lower than those of a nonoffset TFT with mobility drop from 23.8 to 18.3 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$.      

Electrical Properties of Amorphous $hbox{Bi}_{5} hbox{Nb}_{3}hbox{O}_{15}$ Thin Film for RF MIM Capacitors

Amorphous $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}(hbox{B}_{5} hbox{N}_{3})$ film grown at 300 $^{circ}hbox{C}$ showed a high-$k$ value of 71 at 100 kHz, and similar $k$ value was observed at 0.5–5.0 GHz. The 80-nm-thick film exhibited a high capacitance density of 7.8 fF/$muhbox{m}^{2}$ and a low dissipation factor of 0.95% at 100 kHz with a low leakage-current density of 1.23 nA/ $hbox{cm}^{2}$ at 1 V. The quadratic and linear voltage coefficient of capacitances of the $hbox{B}_{5}hbox{N}_{3}$ film were 438 ppm/$hbox{V}^{2}$ and 456 ppm/V, respectively, with a low temperature coefficient of capacitance of 309 ppm/$^{circ}hbox{C}$ at 100 kHz. These results confirmed the potential of the amorphous $hbox{B}_{5}hbox{N}_{3}$ film as a good candidate material for a high-performance metal–insulator–metal capacitors.      

High-Density and Low-Leakage-Current MIM Capacitor Using Stacked $hbox{TiO}_{2}/hbox{ZrO}_{2}$ Insulators

We have fabricated high-$kappa hbox{Ni}/hbox{TiO}_{2}/hbox{ZrO}_{2}/ hbox{TiN}$ metal–insulator–metal (MIM) capacitors. A low leakage current of $hbox{8} times hbox{10}^{-8} hbox{A/cm}^{2}$ at 125 $^{circ}hbox{C}$ was obtained with a high 38- $hbox{fF}/muhbox{m}^{2}$ capacitance density and better than the $hbox{ZrO}_{2}$ MIM capacitors. The excellent device performance is due to the lower electric field in 9.5-nm-thick $hbox{TiO}_{2}/ hbox{ZrO}_{2}$ devices to decrease the leakage current and to a higher $kappa$ value of 58 for $ hbox{TiO}_{2}$ as compared with that of $hbox{ZrO}_{2}$ to preserve the high capacitance density.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Numerical Rate Equation Modeling of a ${sim {hbox {2.1}}-}mu{hbox {m}}-{rm Tm}^{3+}/{rm Ho}^{3+}$ Co-Doped Tellurite Fiber Laser

Judd–Ofelt analysis is performed on measurements of bulk samples of ${rm Tm}^{3+}$ - and ${rm Ho}^{3+}$ -doped tellurite glass from which the host-dependent Judd–Ofelt intensity parameters are extracted. These have then been used to calculate the radiative rates and branching ratios in this particular material system. A rate-equation approach is then used to model an experimentally realized ${sim {hbox {2.1}}},mu{hbox {m}},{rm Tm}^{3+}/{rm Ho}^{3+}$ codoped tellurite fiber laser and extract values of the energy transfer and upconversion rate parameters in ${rm TeO}_{2}-{rm ZnO}-{rm Na}_{2}{rm O}$ (TZN) glass. Excellent agreement is found between simulated and experimental data, which indicates the validity of the approach.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

Low-Voltage Organic Field-Effect Transistor With PMMA/$ hbox{ZrO}_{2}$ Bilayer Dielectric

This paper reports on the application of a bilayer polymethylmethacrylate (PMMA)/ $hbox{ZrO}_{2}$ dielectric in copper phthalocyanine (CuPc) organic field-effect transistors (OFETs). By depositing a PMMA layer on $hbox{ZrO}_{2}$, the leakage of the dielectric is reduced by one order of magnitude compared to single-layer $hbox{ZrO}_{2}$. A high-quality interface is obtained between the organic semiconductor and the combined insulators. By integrating the advantages of polymer and high- $k$ dielectrics, the device achieves both high mobility and low threshold voltage. The typical field-effect mobility, threshold voltage, on/off current ratio, and subthreshold slope of OFETs with bilayer dielectric are $hbox{5.6}timeshbox{10}^{-2} hbox{cm}^{2}/hbox{V} cdot hbox{s}$, 0.8 V, $hbox{1.2} times hbox{10}^{3}$, and 2.1 V/dec, respectively. By using the bilayer dielectrics, the hysteresis observed in the devices with single-layer $hbox{ZrO}_{2}$ is no longer present.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

Fabrication and Characterization of Coplanar Waveguides on Silicon Using a Combination of SiO $_{2}$ and SRO $_{20}$

In this work, the use of silicon rich oxide (SRO) and chemical vapor deposition SiO$_{2}$ double layers as passivation films of coplanar waveguides (CPW) on high resistivity silicon (HR-Si) with an ${hbox{N}}^{+}$ backside is studied. The microwave performance of the fabricated CPWs is evaluated by computing the attenuation loss of the devices in the 0.045–50 GHz frequency range. Experimental results show that the ${hbox{N}}^{+}$ layer can be used without affecting CPW performance. Also, using a combined dielectric layer (SRO$_{20}$ /SiO$_{2}$ ), the attenuation losses are reduced compared to single dielectric layers.      

Improved Electrical Characteristics of Amorphous Oxide TFTs Based on $hbox{TiO}_{x}$ Channel Layer Grown by Low-Temperature MOCVD

We report on the fabrication of n-type thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ channels grown by the metal–organic chemical vapor deposition method with the chamber temperature of 250 $^{circ}hbox{C}$. These TFTs exhibit ideal characteristics with the flat saturation, low subthreshold swing, and narrow hysteresis window, all of which are a clear improvement from our previous work based on $ hbox{TiO}_{2}$ nanoparticles. The $hbox{TiO}_{x}$ film in this letter is identified to be in the amorphous phase from X-ray diffraction analysis, and its carrier density is estimated to be $hbox{2.6} times hbox{10}^{17} hbox{cm}^{-3}$ from the transmission line model and analysis of TFT on-resistance measured at various gate biases and channel lengths.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.